VLSI Design

VLSI Testing


Status
Published

Guest Editors
Sunil Das

VLSI Testing

Articles

  • Special Issue
  • - Volume 4
  • - Article ID 037648

A Modified Approach to Test Plan Generation for Combinational Logic Blocks

Anupam Basu | Dilip K. Banerji | ... | Jay C. Majithia
  • Special Issue
  • - Volume 4
  • - Article ID 080472

Fault Modeling of ECL for High Fault Coverage of Physical Defects

Sankaran M. Menon | Yashwant K. Malaiya | Anura P. Jayasumana
  • Special Issue
  • - Volume 4
  • - Article ID 034084

Switch-level Differential Fault Simulation of MOS VLSI Circuits

Evstratios Vandris | Gerald Sobelman
  • Special Issue
  • - Volume 4
  • - Article ID 029412

Closed Form Aliasing Probability For Q-ary Symmetric Errors

Geetani Edirisooriya
  • Special Issue
  • - Volume 4
  • - Article ID 041420

Erratum

  • Special Issue
  • - Volume 4
  • - Article ID 021276

Guest Editorial

Sunil R. Das
  • Special Issue
  • - Volume 4
  • - Article ID 084045

A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

S. Bandyopadhyay | A. Sengupta | B. B. Bhattacharya
  • Special Issue
  • - Volume 4
  • - Article ID 072136

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits

Kyuchull Kim | Kewal K. Saluja
  • Special Issue
  • - Volume 4
  • - Article ID 075798

On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach

M. Srinivas | L. M. Patnaik
  • Special Issue
  • - Volume 4
  • - Article ID 025839

A Novel Path Delay Fault Simulator Using Binary Logic

Ananta K. Majhi | James Jacob | Lalit M. Patnaik