Si-Qing  Zheng

Dian  Zhou

Preface

We first present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplanthat respects a given slicing tree. The algorithm runs in O(n) time and requires O(n) processors, where n is thenumber of modules. It is based on a new O(n2) sequential algorithm for solving the above problem. We thenpresent a parallel algorithm for finding a set of optimal implementations for a slicing floorplan whose correspondingslicing tree has height O(logn). This algorithm runs in O(n) time using O(logn) processors. Our parallel algorithmsdo not need shared memory and can be implemented in a distributed system.

Cheng-Hsi  Chen

Ioannis G. Tollis

Area Optimization of Slicing Floorplans in Parallel

We discuss a new minimum density objective for spanning and Steiner tree constructions. This formulation ismotivated by the minimum-area layout objective, which is best achieved through balancing the usage of horizontaland vertical routing resources. We present two efficient heuristics for constructing low-density spanning trees andprove that their outputs are on average within small constants of optimal with respect to both tree cost anddensity. Our proof techniques suggest a non-uniform lower bound schema which can afford tighter estimates ofsolution quality for a given problem instance. Furthermore, the minimum density objective can be transparentlycombined with a number of previous interconnection objectives (e.g., minimizing tree radius or skew) withoutaffecting solution quality with respect to these previous metrics. Extensive simulation results suggest that applicationsto VLSI global routing are promising.

C. J. Alpert

J.  Cong

A. B. Kahng

G.  Robins

M.  Sarrafzadeh

On the Minimum Density Interconnection TreeProblem

We present an effective solution to the linear placement problem, which has several applications in the physicaldesign of integrated circuits. Our approach belongs to the class of iterative improvement heuristics. The importantdifference of this new technique from the previous ones is in its moves, and in the order of application of thesemoves. A phase of the algorithm begins with simple moves and gradually shifts towards more complex moves.Phases are repeated as long as further improvement is possible. Our experimental results show that nearly optimalsolutions can be achieved. For a number of examples collected from the literature, our algorithm generatedoptimal solutions.

Youssef  Saab

Cheng-Hua  Chen

An Effective Solution to the LinearPlacement Problem

In this paper, we present a novel concept of the general connectivity among cells. While conventional conceptconsiders direct connections only, the new concept considers both the direct and indirect connections among cellsleading to a model capturing a more precise relationship among cells. Based on the model, a new parallel clusteringapproach is proposed and analyzed. Another new concept of the stable cluster is introduced to improve theclustering result. In conjunction with the clustering process, an investigatory procedure which back tracks thecluster development process to check if all clusters are stable is also developed. Initial test runs, using the newclustering approach for placement, yield an encouraging 21.6% reduction on the number of feed-throughs in acomplex ASIC design.

Wenjun  Zhuang

Yong Ching Lim

Ganesh  Samudra

Neng  Yan

A New Clustering Method Based onGeneral Connectivity

We present in this paper a linear time optimal algorithm for minimizing the density of a channel (with exits) bypermuting the terminals on the two sides of the channel. This compares favorably with the previously knownnear-optimal algorithm presented in [6] that runs in superlinear time. Our algorithm has important applicationsin hierarchical layout design of intergrated circuits. We also show that the problem of minimizing wire length bypermuting terminals is NP-hard in the strong sense.

Yang  Cai

D. F. Wong

Jason  Cong

Channel Density Minimization by Pin Permutation

In this paper we present a new tool for the encoding of multi-level finite state machines based on the concept ofevolution programming. Evolution programs are stochastic adaptive algorithms, based on the paradigm of geneticalgorithms whose search methods model some natural phenomenon: genetic inheritance and Darwinian strife forsurvival. Crossover and mutation rates were tailored to the state assignment problem experimentally. We presentresults over a wide range of MCNC benchmarks which demonstrate the effectiveness of the new tool. The resultsshow that evolution programs can be effectively applied to state assignment.

S.  Muddappa

R. Z. Makki

Z.  Michalewicz

S.  Isukapalli

Pioneer: A New Tool for Coding of Multi-Level FiniteState Machines Based on Evolution Programming

In this paper, we address the technology mapping for RAM-based FPGA. Functional decomposition is appliedto decompose a large function into a set of smaller subfunctions such that each subfunction can be implementedusing a single logic cell. Our system is mainly divided into two parts. The first part is designed specifically fortotally symmetric functions. A Fast-Decompose algorithm based on weight dependency is proposed. The secondpart deals with general functions. We consider some techniques such as output partition, variable partition, don&#39;tcare assignment and encoding to minimize the number of subfunctions derived. Using these techniques together,our tool, Fun-Map, improves the mapping results compared with other tools in terms of area and delay.

Kuo-Hua  Wang

Cheng  Chen

Ting Ting Hwang

Technology Mapping for FPGA Using GeneralizedFunctional Decomposition

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VLSI Design

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VLSI Design

Optimization in VLSI Synthesis and Layout

Optimization in VLSI Synthesis and Layout

Articles

Preface

Area Optimization of Slicing Floorplans in Parallel

On the Minimum Density Interconnection Tree Problem

An Effective Solution to the Linear Placement Problem

A New Clustering Method Based on General Connectivity

Channel Density Minimization by Pin Permutation

Pioneer: A New Tool for Coding of Multi-Level Finite State Machines Based on Evolution Programming

Technology Mapping for FPGA Using Generalized Functional Decomposition