VLSI Design

VLSI Design / 1994 / Article
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Optimization in VLSI Synthesis and Layout

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Volume 2 |Article ID 063707 | https://doi.org/10.1155/1994/63707

Cheng-Hsi Chen, Ioannis G. Tollis, "Area Optimization of Slicing Floorplans in Parallel", VLSI Design, vol. 2, Article ID 063707, 14 pages, 1994. https://doi.org/10.1155/1994/63707

Area Optimization of Slicing Floorplans in Parallel


We first present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplan that respects a given slicing tree. The algorithm runs in O(n) time and requires O(n) processors, where n is the number of modules. It is based on a new O(n2) sequential algorithm for solving the above problem. We then present a parallel algorithm for finding a set of optimal implementations for a slicing floorplan whose corresponding slicing tree has height O(logn). This algorithm runs in O(n) time using O(logn) processors. Our parallel algorithms do not need shared memory and can be implemented in a distributed system.

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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