Gregory D. Peterson

Ethan Farquhar

Benjamin Blalock

Selected Papers from the Midwest Symposium on Circuits and Systems

Nonlinear signal processing is necessary in many emerging applications where form factor and power are at a premium. In order to make such complex computation feasible under these constraints, it is necessary to implement the signal processors as analog circuits. Since analog circuit design is largely based on a linear systems perspective, new tools are being introduced to circuit designers that allow them to understand and exploit circuit nonlinearity for useful processing. This paper discusses two such tools, which represent nonlinear circuit behavior in a graphical way, making it easy to develop a qualitative appreciation for the circuits under study.

K. Odame

P. E. Hasler

Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping

A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.

Yan Zhu

U-Fat Chio

He-Gong Wei

Sai-Weng Sin

Seng-Pan U

R. P. Martins

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

An accurate ultrasonic range finder employing Sliding Discrete Fourier Transform (SDFT) based restructured phase-locked loop (RPLL), which is an improved version of the recently proposed integrated phase-locking scheme (IPLL), has been expounded. This range finder principally utilizes amplitude-modulated ultrasonic waves assisted by an infrared (IR) pilot signal. The phase shift between the envelope of the reference IR pilot signal and that of the received ultrasonic signal is proportional to the range. The extracted envelopes are filtered by SDFT without introducing any additional phase shift. A new RPLL is described in which the phase error is driven to zero using the quadrature signal derived from the SDFT. Further, the quadrature signal is reinforced by another cosine signal derived from a lookup table (LUT). The pulse frequency of the numerically controlled oscillator (NCO) is extremely accurate, enabling fine tuning of the SDFT and RPLL also improves the lock time for the 50&#x2009;Hz input signal to 0.04&#x2009;s. The percentage phase error for the range 0.6&#x2009;m to 6&#x2009;m is about 0.2&#x00025;. The VHDL codes generated for the various signal processing steps were downloaded into a Cyclone FPGA chip around which the ultrasonic ranger had been built.

P. Sumathi

P. A. Janakiraman

FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme

A new technique is presented for biasing of analog circuits. The biasing design begins with local biasing of the nonlinear components (transistors), done according to the pre-specified operating points (OPs) and for the best performance of the circuit. Next, the transistors are replaced with their linear models to perform the AC design. Upon finishing with the AC design we need to move from the local biasing to global (normal) biasing while the OPs are kept unchanged. Here fixators&#8212;nullators plus sources&#8212;are shown to be very instrumental and with norators&#8212;as the place holders for the DC supplies in the circuit&#8212;they make pairs. The solution of the circuit so prepared provides the DC supplies at the designated locations in the circuit. The rules to engage in circuit analysis with fixator-norator pairs are discussed, and numerous pitfalls in this line are specified. Finally, two design examples are worked out that clearly demonstrate the capability and power of the proposed technique for biasing any analog circuit.

Reza Hashemian

Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs

The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38&#37; and delay uncertainty from process variations by 35&#37; in comparison with a state-of-the-art commercial optimization tool.

Kumar Yelamarthi

Chien-In Henry Chen

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such as Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx XC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the reconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>π</mml:mi></mml:math>-estimator for the Cray XD1. The RC Monte Carlo <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>π</mml:mi></mml:math>-estimator shows a 19.1<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mo>×</mml:mo></mml:math> speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1. In this paper we describe the FPGA implementation for HASPRNG and a <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>π</mml:mi></mml:math>-estimator example application exploiting the fine-grained parallelism and mathematical properties of the SPRNG algorithm.

JunKyu Lee

Robert J. Harrison

Robert J. Hinde

Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronous
design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested <svg style="vertical-align:-0.17555pt;width:27.475px;" id="M1" height="11.1" version="1.1" viewBox="0 0 27.475 11.1" width="27.475" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(1.25,0,0,-1.25,0,11.1)"><g transform="translate(72,-63.12)"><text transform="matrix(1,0,0,-1,-71.95,63.35)"><tspan style="font-size: 12.50px; " x="0" y="0">0</tspan><tspan style="font-size: 12.50px; " x="6.2515001" y="0">.</tspan><tspan style="font-size: 12.50px; " x="9.3772497" y="0">2</tspan><tspan style="font-size: 12.50px; " x="15.62875" y="0">5</tspan></text></g></g></svg> <svg style="vertical-align:-2.29482pt;width:21.799999px;" id="M2" height="10.175" version="1.1" viewBox="0 0 21.799999 10.175" width="21.799999" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(1.25,0,0,-1.25,0,10.175)"><g transform="translate(72,-63.86)"><text transform="matrix(1,0,0,-1,-71.95,66.2)"><tspan style="font-size: 12.50px; " x="0" y="0">𝜇</tspan><tspan style="font-size: 12.50px; " x="7.6018238" y="0">m</tspan></text></g></g></svg> technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

Bo Marr

Jason George

Brian Degnan

David V. Anderson

Paul Hasler

Error Immune Logic for Low-Power Probabilistic Computing

Recent advances in Field-Programmable Gate Array (FPGA) technology make reconfigurable computing using FPGAs an attractive platform for accelerating scientific applications. We develop a deeply pipelined and parallel architecture for Quantum Monte Carlo simulations using FPGAs. Quantum Monte Carlo simulations enable us to obtain the structural and energetic properties of atomic clusters. We experiment with different pipeline structures for each component of the design and develop a deeply pipelined architecture that provides the best performance in terms of achievable clock rate, while at the same time has a modest use of the FPGA resources. We discuss the details of the pipelined and generic architecture that is used to obtain the potential energy and wave function of a cluster of atoms.

Akila Gothandaraman

G. Lee Warren

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Dedicated hardware implementations of artificial neural networks promise to provide faster, lower-power operation when compared to software implementations executing on microprocessors, but rarely do these implementations have the flexibility to adapt and train online under dynamic conditions. A typical design process for artificial neural networks involves offline training using software simulations and synthesis and hardware implementation of the obtained network offline. This paper presents a design of block-based neural networks (BbNNs) on FPGAs capable of dynamic adaptation and online training. Specifically the network structure and the internal parameters, the two pieces of the multiparametric evolution of the BbNNs, can be adapted intrinsically, in-field under the control of the training algorithm. This ability enables deployment of the platform in dynamic environments, thereby significantly expanding the range of target applications, deployment lifetimes, and system reliability. The potential and functionality of the platform are demonstrated using several case studies.

Saumil G. Merchant

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

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Selected Papers from the Midwest Symposium on Circuits and Systems

Selected Papers from the Midwest Symposium on Circuits and Systems

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