Data Link Layer Considerations for Future 100 Gbps Terahertz Band Transceivers

Table 2

Required hardware resources for selected forward error correction implementations.

Implementation	Reference	Max. Clk. MHz]	LUT area	FPGA/speed grade
Xilinx Viterbi decoder	[8]	286	2525	Virtex7/-1
Xilinx Viterbi decoder	[8]	403	2525	Virtex7/-3
Creonic Viterbi decoder	[28]	250	2984	Virtex6/-1
Creonic Viterbi decoder	[28]	142	3054	Spartan6/-2
IHP Viterbi decoder	[20]	170	12000	Virtex7/-2
Xilinx RS decoder	[8]	294	765	Virtex7/-1
Xilinx RS decoder	[8]	410	765	Virtex7/-3
Xilinx RS encoder	[24]	388	260	Virtex7/-1
Xilinx RS encoder	[24]	598	260	Virtex7/-3
IHP RS decoder	[20]	285	2585	Virtex7/-2
IHP RS encoder	[20]	457	200	Virtex7/-2
IHP RS decoder	[20]	270	5554	Virtex7/-2