FPGA Implementation of UFMC Based Baseband Transmitter: Case Study for LTE 10MHz Channelization

Table 3

Result comparison.

Ref.	FPGA; Device	Slice Reg.	Slice LUTS	DSP48	BRAMs	Processing Time	Latency; ()
[21]	Zynq-7	2720	3711 + (876 for RAM) = 4587	20	-	2.33 for 512 subcarriers	3.65
[22]	Kintex-7	11300	7990	30	19	66.7 for 72 subcarriers	-
Our Solution	Virtex-7	910	1133	64	3	1.417 for 12 carriers	2.835