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(b)
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Figure 18: (a) Digitally controlled, load modulated power-DAC architecture for linear and highly efficiency mm-Wave PA design [19]; (b) schematic of the 33–46 GHz watt-class PA array prototype; (c) schematic of the two-stage 45 nm SOI CMOS stacked PA unit-cell used in the watt-class PA array prototype; (d) chip microphotograph of the 33–46 GHz watt-class PA array prototype. Chip dimensions are 3.2 mm × 1.3 mm without pads © 2013 IEEE.