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Wireless Communications and Mobile Computing
Volume 2018, Article ID 8712414, 8 pages
https://doi.org/10.1155/2018/8712414
Research Article

A Novel Quadrature-Tracking Demodulator for LTE-A Applications

Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, 2 Jhuoyue Rd., Nanzih, Kaohsiung City 811, Taiwan

Correspondence should be addressed to Kang-Chun Peng; wt.ude.tsufkn@gkpretep

Received 27 July 2017; Accepted 2 December 2017; Published 2 January 2018

Academic Editor: Chaojiang Li

Copyright © 2018 Kang-Chun Peng and Chan-Hung Lee. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This work develops an advanced quadrature-tracking demodulation technique for coherently demodulating the orthogonal frequency-division multiplexing (OFDM) signal of LTE-A systems. To overcome the fact that traditional coherent demodulators are extremely sensitive to the quadrature imbalance of a system, especially an OFDM system, the proposed architecture uses a novel quadrature phase-locked loop (QPLL) to track simultaneously the in phase (I-phase) and the quadrature phase (Q-phase) of the received signal. This advanced quadrature-tracking demodulator is realized using TSMC 0.18 μm CMOS technology and hybrid circuits. Experimental results indicate that the developed quadrature-tracking demodulator, which operates at 2.1~2.5 GHz, can effectively demodulate an 18 Mbps LTE-A signal, even with a 15 degree quadrature imbalance.

1. Introduction

Most wireless communication systems use coherent demodulation, mainly because the quality of coherent demodulation is much better than that of non-coherent demodulation [1]. Traditional coherent demodulators are based on an RF quadrature demodulator. But the RF coherent circuits are usually complex and power-hungry [2]. To simplify the receiver’s circuitry, various phase-locked loop (PLL)-based coherent demodulators are adopted in wireless communication systems. The most well-known PLL-based coherent demodulator has the Costas architecture [1, 35]. As depicted in Figure 1, this architecture uses a single PLL with two feedback loops. These two feedback loops demodulate the in-phase (I-phase) signal and quadrature-phase (Q-phase) signals, respectively. The demodulated signals are combined, and then tune the voltage-controlled oscillator (VCO) to track the frequency of the carrier signal. However, both the traditional quadrature demodulator and the Costas-coherent demodulator face the problem of quadrature imbalance of RF signal. Quadrature imbalance of RF signal arises from both the quadrature transmitter and the quadrature receiver. Previous investigations have showed that a slight 2.5 degree quadrature imbalance significantly degrades the demodulation quality of an OFDM signal, which is extensively used in LTE-A systems [6, 7]. Although the conventional Costas-coherent demodulator has two feedback loops for demodulation, the single-VCO design prevents tracking of more than one phase of a received signal.

Figure 1: Traditional Costas demodulator.

We [8] previously presented an alternative coherent polar demodulator without the quadrature imbalance problem of receiver. As presented in Figure 2, the received signal is divided into two paths. One of these paths uses injection-locked oscillators (ILO) to extract the phase-modulated carrier signal and the phase information. The extracted phase-modulated carrier is then mixed with the received signal along another path. The mixing cancels out the phase information of these two input signals, and then the envelope information of the received signal is exported. The baseband processor then recovers the baseband signal from both the demodulated phase and the envelope information. However, the quadrature imbalance that is caused by the RF transmitter remains in the received signal.

Figure 2: Polar demodulator.

To overcome the quadrature imbalance problem, some works directly trimming or adjusting their RF circuits [9]. However, these are impractical. Another solution is based-on digital-signal process (DSP) technique. [10] and [11] respectively uses the pilot signal and a special tone to train the DSP in receiver to find out and then correct the quadrature imbalance. [9, 12] utilize adaptive algorithms to estimate the quadrature error and then compensate demodulated signal. Although these adaptive algorithms theoretically can reduce the quadrature imbalance to less than 1 degree, they take a very long computation time with about 105 iterations. To speed up the tracking process, this work proposes a novel quadrature-tracking demodulator which can real-time track the quadrature error.

2. Quadrature-Tracking Demodulator

To eliminate the extreme sensitivity of traditional coherent demodulation to the quadrature phase imbalance, this work proposes a novel quadrature phase-locked loop (QPLL)-based coherent demodulator. As depicted in Figure 3(a), the proposed QPLL is based mainly on two identical PLLs with a channel-preset frequency synthesizer. Unlike the traditional Costas-coherent demodulator which uses a single-ended VCO, the QPLL-based demodulator utilizes a novel quadrature voltage-controlled oscillator (QVCO). As presented in Figure 3(b), the QVCO is formed by cross-coupling two identical differential VCOs. The tuning ports of these two VCOs are independent of each other, rather than connected. One performs I-phase tracking in the QPLL while the other performs Q-phase tracking. Under the initial condition of demodulation, the two tuning ports of the QVCO are shorted to make the QPLL act as a single PLL to lock the carrier frequency of the received signal. Since the effective detection range of a mixer-based phase detector is limited by ±90 degree [13], as depicted in Figure 4, an additional channel-preset frequency synthesizer is required. The additional frequency synthesizer uses an all-digital phase-frequency detector (PFD) to detect a large phase variance of up to ±360 degree. Therefore, the QPLL can track both the frequency and the phase of the received signal. After the frequency of the received signal has been locked, the channel-preset frequency synthesizer is turned off to save power and the two VCO tuning ports are disconnected, as presented in Figure 5. The QPLL can then track in real time and demodulate both the I-phase and the Q-phase of the received signal. According to PLL theory, a PLL-based demodulator attenuates the demodulated signal within the loop bandwidth of the PLL [13]. Therefore, the proposed architecture is especially suited to OFDM systems because the DC-subcarrier of the OFDM signal, as depicted in Figure 6, is not used in the LTE-A system, to mitigate the DC-offset problem [14]. Therefore, the proposed advanced QPLL-based demodulation technique can coherently demodulate the OFDM signal without attenuation if the loop bandwidth of the PLL is designed to be less than the sub-carrier space.

Figure 3: Proposed (a) quadrature-tracking demodulator, and (b) QVCO.
Figure 4: Effective phase-detection range of a mixer-based phase detector.
Figure 5: Proposed demodulator under quadrature-tracking and demodulating conditions.
Figure 6: Sub-carrier spectrums of OFDM signal in LTE-A system.

3. System Analysis

To analyze the proposed quadrature-tracking demodulator in the time domain, the received signal is assumed to be where and denote baseband signals, and is the frequency error; and are the phase errors of the I-phase signal and the Q-phase signal, respectively. After down-mixing, the signal at nodes A and B in the circuit that is displayed in Figure 5 is derived aswhere are the I-phase and -phase phase errors between the transmitter and the receiver. Since the loop bandwidth of the PLL must be narrower than the sub-carrier space of the OFDM signal, the signal at nodes C and D of the circuit in Figure 5 are derived asAccording to PLL theory, the negative-feedback mechanism makes , , and equal zero. Under these conditions, the QPLL-based demodulator locks both the frequency and the phase of the received RF signal.

To extract the demodulated baseband signals from the QPLL-based demodulator, two additional low-pass filters are used at the output of phase detectors. The cut-off frequency of the filter must exceed the top of the frequency band of the baseband signal. The signals at nodes E and F, shown in Figure 5 are derived asSince , , and are zero when the PLL locks the frequency and phase of the received signal, the demodulated -phase signal and -phase signal are found asEquations (6) indicate that the novel demodulator can effectively demodulate the received signal without distortions, which would otherwise be caused by the quadrature-imbalance.

To further analyze the frequency response of the proposed demodulator, a frequency domain linear model is developed, as presented in Figure 7. and represent the frequency responses of the loop filters. and represent the sensitivities of the QVCO and mixer-based phase detector, respectively. represents the phase noise of the QVCO.represent the I-phase and Q-phase of the received signal, respectively, where and are the quadrature phase errors. and denote the phases of the demodulated signals, respectively, and are given bywhere is the error transfer function of the QPLL, andAccording to final value theory, the output quadrature errors and are zero when the quadrature phase errors and are constant [15]. Under these conditions, Eqs. (8), can be simplified asFigure 8 plots the frequency response of , where represents the loop bandwidth of the QPLL and is the cut-off frequency of the LPF. The should be designed to be narrower than the frequency gap between subcarriers to prevent distortion. should equal the channel bandwidth of the system to enable channel selection. From the spectrum of the OFDM sub-carriers and the frequency response of the demodulator in Figure 8, the proposed architecture can coherently demodulate the received OFDM signal without any distortion. Moreover, the phase noise from the QVCO can be effectively suppressed by the demodulator in the loop bandwidth , too.

Figure 7: Linear phase model of proposed quadrature-tracking demodulator.
Figure 8: Frequency response of proposed quadrature tracking demodulator.

Figures 9(a) and 9(b) presents the system-level simulation result of demodulated spectrum of traditional quadrature demodulator and the proposed quadrature tracking demodulator, respectively. In the simulation, the modulation type is set to be OFDM with 64 sub-carriers. These results show that the demodulated spectrum of traditional quadrature demodulator is significantly degraded as the quadrature imbalance increasing from 0 degree to 15 degree. Under the same condition, the demodulated spectrum of the proposed quadrature tracking demodulator shows a very slight decline.

Figure 9: Demodulated spectrum of (a) traditional quadrature demodulator and (b) proposed quadrature tracking demodulator.

4. Experimental Results

The QVCO of the proposed demodulator was implemented using TSMC 0.18 μm CMOS technology. Figure 10(a) shows the circuit design of the CMOS QVCO. Generally, a VCO with internal NMOS cross-coupled pairs has a wider operating range but a poorer phase noise performance than the one with internal PMOS cross-coupled pairs [18]. Based on consideration of both the phase noise performance and operating range, the internal complementary cross-coupled pair is used. To realize quadrature outputs, external cross-coupling between two identical differential VCOs are required so four additional NMOS are designed to be parallel to the original NMOS cross-coupled pair. The outputs of two identical differential VCOs then cross-couple to each other via the gates of the additional NMOSs. These internal and external couplings of the VCOs force the four outputs signal quadrature each other. Since the QPLL must separately track the I-phase and the Q-phase of the received signal, the QVCO is designed to have two tuning ports, as presented in Figure 10(a). This architecture enables the quadrature of the QVCO to be slightly adjusted using the two independent tuning ports.

Figure 10: (a) Circuit and (b) CMOS chip of the QVCO.

Figure 10(b) displays the implemented CMOS QVCO chip. The measured power consumption is less than 8.9 mW. The operating range and output power of the CMOS QVCO are measured and presented in Figure 11(a). The CMOS QVCO can operate from 2.1 to 2.5 GHz with a mean output power of around 2 dBm, which is sufficiently high to drive passive double-balance mixers for phase detection. The measured output power of the QVCO also exhibits very good flatness of better than 2 dB over the wide operating range. Figure 11(b) plots the measured phase noise of the CMOS QVCO. The phase noise is lower than −113 dBc/Hz and −137 dBc/Hz at 1 MHz and 10 MHz offset frequency, respectively. Table 1 shows the performance comparison between 2.4 GHz CMOS QVCOs, where the figure of merit (FoM) is given by [19]The comparison shows that the implemented QVCO achieves a lowest phase noise and power consumption, and consequently results in a better FoM over the other QVCOs.

Table 1: Performance Comparison of 2.4 GHz QVCOs.
Figure 11: Measured (a) operating range and output power, and (b) phase noise of CMOS QVCO of demodulator.

The proposed quadrature-tracking demodulator is implemented with the designed CMOS QVCO, as presented in Figure 12. The channel-preset frequency synthesizer of the demodulator is implemented using a consumer IC PE3336, produced by Peregrine. The phase detectors are the ZX05-C42 S+ model from Mini-Circuits. The LPFs are the SLP-10.7+ model, also from Mini-Circuits, and have a 3 dB bandwidth of 14 MHz. The loop bandwidth of the QPLL is designed to be 10 kHz. The received LTE-A signal of the receiver is generated using a Keysight MXA vector signal generator (VSG) with Keysight Signal Studio. The data rate of the LTE-A signal is set to be 18 Mbps. The sub-carrier space is set to 156.25 kHz, which greatly exceeds the 10 kHz loop bandwidth of the QPLL.

Figure 12: Implemented quadrature-tracking de-modulator.

Figures 13(a) and 13(b) presents the demodulated I-phase and Q-phase waveforms, respectively. To confirm the quadrature-tracking performance of the implemented demodulator, the quadrature-imbalance of the LTE-A signal is manually adjusted in the signal studio. As the quadrature-imbalance is increased from 0 degree to 15 degree, both the I-phase and the Q-phase waveforms are degraded slightly revealing that the implemented quadrature-tracking demodulator can effectively demodulate the LTE-A signal even if the signal has a 15° quadrature-imbalance.

Figure 13: Demodulated (a) I-phase and (b) Q-phase baseband waveforms when received LTE-A signal has a quadrature imbalance of 15°.

Figure 14 shows the measured signal to noise and distortion ratio (SINAD) degradation of the implemented demodulator as a function of quadrature imbalance. Comparing with the well-known signal to noise ratio (SNR), SINAD further considers the combining effect of both noise and distortion. Therefore, the SINAD is usually used to evaluate performance of RF receivers [20]. SINAD is defined aswhere , , , and represents the power of the ideal signal, distorted signal, noise, and distortion, respectively. The measured results show that the SINAD slightly degrade as the quadrature imbalance increase from 0 degree to 15 degree. As the quadrature imbalance is 15 degree, the SINAD of the implemented quadrature-tracking demodulator is about 18.761 dB which is acceptable for most wireless communication applications.

Figure 14: Measured SINAD of the implemented quadrature-tracking demodulator.

5. Conclusion

In this work, a novel quadrature tracking demodulator for LTE-A applications was implemented. The 2.1~2.5 GHz QPLL-based demodulator can effectively demodulate an 18 Mbps LTE-A signal with a quadrature-imbalance of up to 15 degrees. This remarkable quadrature-tracking ability makes the novel demodulator well suited to LTE-A systems or even more advanced communication systems.

Conflicts of Interest

The authors declare that there is no conflicts of interest regarding the publication of this paper

Acknowledgments

The authors would like to thank the Ministry of Science and Technology (101-2221-E-327-029) for providing research funding. The authors would also like to thank the National Chip Implementation Center, Hsinchu, Taiwan, for providing the CMOS foundry service.

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