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Wireless Communications and Mobile Computing
Volume 2018, Article ID 8928761, 6 pages
https://doi.org/10.1155/2018/8928761
Research Article

Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code

Key Laboratory of Universal Wireless Communications, Ministry of Education, Beijing University of Posts and Telecommunications, Beijing 100876, China

Correspondence should be addressed to Zhenzhen Liu; nc.ude.tpub@uilzz

Received 24 November 2017; Revised 8 March 2018; Accepted 27 March 2018; Published 3 May 2018

Academic Editor: Zesong Fei

Copyright © 2018 Zhenzhen Liu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In this paper, a three-dimensional polar code (3D-PC) scheme is proposed to improve the error floor performance of parallel concatenated systematic polar code (PCSPC). The proposed 3D-PC is constructed by serially concatenating the PCSPC with a rate-1 third dimension, where only a fraction of parity bits of PCSPC are extracted to participate in the subsequent encoding. It takes full advantage of the characteristics of parallel concatenation and serial concatenation. In addition, the convergence behavior of 3D-PC is analyzed by the extrinsic information transfer (EXIT) chart. The convergence loss between PCSPC and different provides the reference for choosing the value of for 3D-PC. Finally, the simulation results confirm that the proposed 3D-PC scheme lowers the error floor.

1. Introduction

The novel concept of parallel concatenated systematic polar code (PCSPC) was first put forward in [1]. PCSPC scheme consists of two systematic polar codes (SPCs) [2]. It has performance advantage with respect to original SPC. In [3], the extrinsic information transfer (EXIT) charts of different length SPC have been given. As a promotion of the above EXIT chart results, the convergence behavior of PCSPC can be analyzed. It can be observed that SPC with larger code length leads to narrower opening. Therefore, it is difficult for PCSPC with large code length SPCs to converge at low error rate. The motivation of our work is to solve this problem.

As we know, there is error floor for turbo code (TC) at block error rate (BLER) around [4]. In order to improve the performance of TC in the error floor region, three-dimensional turbo code (3D-TC) has been studied in [57]. 3D-TC scheme was proposed by serially concatenating a rate-1 cyclic recursive systematic convolutional (CRSC) code to conventional TC. It is important to note that only a fraction of parity bits from TC are extracted to participate in the encoding again. Compared with conventional TC, 3D-TC scheme has larger minimum distance. Therefore, 3D-TC improves the error floor performance greatly. In addition, the influence of of 3D-TC on convergence threshold and minimum distance has been researched in [6, 7].

It is known from the literature that serial concatenated code has larger minimum distance with respect to parallel concatenated code; however, its convergence threshold is worse than that of parallel concatenation [8]. Meanwhile, inspired by the idea in [7], 3D polar code (3D-PC) scheme is proposed to improve the error floor performance of PCSPC in this paper. It makes full use of the features of parallel concatenation and serial concatenation. 3D-PC is constituted by adding a rate-1 CRSC code to PCSPC. And only a fraction of parity bits of PCSPC are sent to the third encoder. Moreover, the convergence behavior of 3D-PC is analyzed by EXIT chart method [9]. It can be utilized to guide the choice of which is an important parameter that affects the performance of 3D-PC. Simulation results corroborate the effectiveness of 3D-PC scheme to improve the low error rate performance.

The paper is organized as follows. Section 2 reviews systematic polar code and EXIT chart. 3D-PC scheme is proposed in Section 3. In Section 4, convergence analysis of 3D-PC is presented. The simulation results are shown in Section 5. Section 6 concludes this paper.

2. Preliminaries

2.1. Systematic Polar Code

Polar code is a capacity-achieving channel code which was proposed by Arıkan in [10]. Given code length and code rate , the reliabilities of subchannels can be obtained by Gaussian approximation method [11] or other construction algorithms. Then the subchannels with high reliability are used to transmit information bits, and other subchannels are utilized to deliver frozen bits. Let set denote the indexes of those high reliability subchannels. Supposing that the input sequence is given, the codeword of polar code can be obtained bywhere is the generator matrix, denotes the bit-reversal permutation matrix, denotes the -th Kronecker product, and .

Since the input source sequence can be decomposed into two parts and , the codeword in (1) can be written aswhere is the information bits, denotes the complement of , and consists of the rows of with indices in .

Systematic polar code is constructed based on polar code [2]. Assume that -elements set denotes the indexes of system bits; then denotes system bits and is the check bits. Equation (2) can be rewritten aswhere denotes the submatrix of with row indexes in and column indexes belonging to .

As to SPC, the systematic bits are known and are also known and set to zero; thus can be calculated according to (3):

Further, the check bits can be computed by (4):

Here, the codeword of SPC is achieved.

2.2. EXIT Chart

EXIT chart [9] is an efficient convergence analysis tool for the iterative decoding structure. It tracks the average mutual information of constituent decoders.

We use and to denote the transmitted bits and the corresponding a priori information, respectively. And is modeled as an independent Gaussian random variable with the following expression:

withwhere is a Gaussian random variable with mean zero and variance . Under the above assumption, the mutual information between transmitted bits and a priori information can be written as

Assume that extrinsic information is denoted by . The mutual information between and is calculated aswhere is the probability distribution function given condition . It can be obtained by Monte Carlo simulation.

3. Proposed 3D Polar Code Scheme

3.1. Encoding Structure

In short, 3D-PC scheme can be regarded as a concatenation of the inner code and outer code, PCSPC. The encoding structure of 3D-PC is illustrated in Figure 1. First of all, the input information sequence with length is encoded by parallel concatenated systematic polar encoder. The component encoders of PCSPC are written as and , respectively. Both of them are systematic polar encoders. We use and to denote the parity bits sequence of and , respectively. Further, the codeword can be obtained by taking the bits from and alternatively. The fraction of is interleaved by the interleaver and sent to the postencoder for encoding, where is named as permeability rate. And codeword is output by the postencoder . The parity bits chosen for encoding follow a certain puncturing pattern with length . The fraction of is passed to the channel straightly, denoted by . The patterns and are complementary. Furthermore, the last codeword of 3D-PC with code length is obtained by combining the input sequence , the parity sequence , and the parity sequence . Here the code rate of 3D-PC is calculated by . In order to achieve higher code rate, it is need to puncture some parity bits from or . Since contains more information, is first taken into consideration.

Figure 1: 3D polar encoder.

For complexity and performance reasons, the selected encoder should meet some requirements: its decoder is as simple as possible, its decoder inputs soft information and outputs soft information, and its decoder should not introduce too much error [5]. As a result, a rate-1 cyclic recursive systematic convolutional encoder with generator polynomial is selected as the encoder [6].

In literature [5, 6], the interleavers and have been well designed to increase the minimum distance. Because the design of interleaver has a great influence on the performance of TC. While the effect of interleaver on polar code is not so obvious, random interleaver is considered in this 3D polar encoding structure for convenience.

In this paper, regular puncturing pattern is applied to . If is adopted to with length , there are altogether ones in the period . The bits of corresponding to the positions of ones are not punctured. For example, assume that and ; then every fourth bit of and is extracted and sent to for encoding again. According to the relationship between and , it is easy to obtain . If we apply to , then the bits which are reserved are sent to the channel.

3.2. Decoding Structure

In general, a concatenated code can be decoded by the iterative decoding structure. The decoding diagram of 3D-PC is shown in Figure 2. The sequence is received from channel and is demultiplexed into three parts, , , and . The corresponding channel logarithm likelihood ratios (LLRs) are denoted by , , and . Later they participate in the subsequent decoding. The decoders , , and are corresponding to encoders , , and , respectively.

Figure 2: The iterative decoding structure of 3D-PC.

First, from channel and from and are fed to for decoding. Then the extrinsic information is deinterleaved, combined with and demultiplexed into two parts, and . The obtained and are regarded as channel LLRs of parity bits and assist and in decoding, respectively. For outer decoder, the extrinsic information related to is exchanged between and because both the input information of and that of are from . Additionally, the extrinsic information, and , of parity bits which is output by and goes through the following operations: multiplex, puncture, and interleave. Then extrinsic LLR information is obtained and delivered to as a priori information at next iteration. The extrinsic LLR information of part parity bits is exchanged between inner decoder and outer decoder as framed in Figure 2. The exchange procedure is terminated when the given out-loop iteration number is reached and the decision is made by the LLR information of .

Since it is needed to exchange extrinsic information between and , the decoder adopted should meet the soft-in-soft-out (SISO) requirement. As to the decoding of SPC, there are two SISO decoding algorithms, belief propagation (BP) decoding [12] and soft cancellation (SCAN) decoding [13]. Therefore, BP decoder and SCAN decoder can be considered for the decoders and .

As to the decoding of tail-biting convolutional code, the optimal algorithm is maximum a posteriori probability (MAP) decoding algorithm, but its complexity is very high. Two suboptimal MAP decoding algorithms have been proposed for tail-biting convolutional code, tail-biting BCJR (TB-BCJR), and A3 [14]. Afterwards, a less complexity MAP algorithm has been presented to decode tail-biting convolutional code [15]. Therefore, the TB-BCJR, A3 algorithms and the low complexity MAP algorithm can be chosen as the candidate schemes for decoder.

4. Convergence Behavior Analysis

In this part, EXIT chart is utilized to analyze the convergence threshold of 3D-PC. In Figure 3, the simplified decoding structure for the calculation of EXIT chart is given. In Figure 3, denotes the average mutual information between and , denotes the average mutual information between and , denotes the average mutual information between and , and denotes the average mutual information between and . The detailed calculation processes of EXIT chart curve are presented as follows:(1)Given signal to noise ratio (SNR), and ; then the a priori information can be obtained by the assumed model [9] and is sent for the inner decoder .(2)Monte Carlo simulation based on is performed to get the distributions of of (10).(3)Then is calculated by substituting into (10).(4)Traverse at a certain step size in a certain internal and calculate the corresponding . Then the curve which depicts the relation between and is obtained.

Figure 3: Simplified decoding structure for EXIT chart analysis.

Likewise, can be got by the above processes. The differences are that the decoder for Monte Carlo simulation is outer decoder other than , is given, and the transmitted bits are instead of .

Figure 4 gives the EXIT chart of 3D-PC with two configurations, and . The EXIT chart curves of the outer code and inner code are denoted by solid curves and dash curves, respectively. From Figure 4, it can be seen that there is an opening between the EXIT chart curves of inner code and outer code for both configurations. Since there is no disjoint for each pair of EXIT chart curves, the decoding of 3D-PC can reach convergence. In general, the EXIT chart curves can be depicted with the variety of SNR. The convergence threshold is the SNR at which the tunnel between EXIT chart curves pairs is very narrow. As to 3D-PC with and , the convergence threshold is 3.4 dB. Table 1 lists the convergence thresholds of 3D-PC under different . The simulation frames for Monte Carlo simulation are .

Table 1: Convergence thresholds of 3D-PC.
Figure 4: EXIT chart of , , 3D-PC, SNR = and of , , 3D-PC, SNR = .

From Table 1, it can be observed that the convergence threshold increases with the increase of . Compared with the best convergence threshold when is , the convergence loss under and is relatively small. Therefore, those two configurations are set to 3D-PC.

5. Simulation Results

In Figure 5, the BLER performance of 3D-PC is given. The underlying channel is additive white Gaussian noise (AWGN) channel. The input block size is set to . The code rate of the component SPC is . However, it is noteworthy that the output of the component SPC is parity bits. And the total code rate of 3D-PC is . The interleavers and used for simulation are random interleavers. The internal iteration number of outer decoder is and the iteration number between the inner decoder and the outer decoder is equal to . In addition, SCAN decoding algorithm is utilized for the decoding of SPC and the CRSC code is decoded by low complexity MAP decoding [15]. Different permeability rates are set to 3D-PC scheme, such as and .

Figure 5: Performance comparison between PCSPC and 3D-PC. For both PCSPC and 3D-PC, the input information length and code rate of them are and , respectively.

As a comparison scheme, the performance of PCSPC is also given in Figure 5. The constituent codes are SPCs with code rate and code length . Under this configuration, the total code rate of PCSPC is which is the same as that of 3D-PC. The SCAN decoding algorithm is applied to decode the component codes. For fair comparison, total iteration numbers between the PCSPC component decoders are required to set the same for both the conventional PCSPC and the proposed 3D-PC scheme. Thereafter the outer loop number between the two constituent decoders is equal to .

By observing Figure 5, it can be found that the performance in water region is lost for 3D-PC with respect to PCSPC. This phenomenon is accordant with the analysis in Section 4. That is, the convergence threshold becomes larger with the increase of . In addition, 3D-PC has better BLER performance than PCSPC in low error rate. For PCSPC, error floor phenomenon begins at about BLER . However, the error floor does not appear around BLER for 3D-PC. In other words, the error floor is lowered by the proposed 3D-PC scheme. The reason may be that 3D-PC has lager minimum distance compared with PCSPC.

In addition to performance, complexity is also important. As to the conventional PCSPC [1], the computation complexity is written aswhere is iteration number between the component decoders and is the code length of component systematic polar code. For the proposed 3D scheme, it includes not only the complexity of PCSPC decoder, but also the complexity of tail-biting convolutional code decoder [15]. Comprehensively, the complexity is aboutwhere is the out-loop iteration number, is the memory element of tail-biting convolutional code, is the code length of component polar code, and is the permeability rate. In (12), and denote the complexity of outer decoder and inner decoder in one outer iteration, respectively. Since the inner iteration number between the PCSPC component decoders is , the complexity of outer decoder is according to (11). As to Log-MAP algorithm, the complexity can be regarded as the metric updates in the trellis nodes. Corresponding to (12), denotes the metric updates per trellis node, is the state numbers, and denotes the input information length of tail-biting convolutional code which can be known from 3D polar encoder (refer to Section 3).

In this paper, and are set the same to ensure that the total iteration number between the PCSPC component decoders is the same. Moreover, the increased complexity is which is brought by inner decoder. Since the memory of the tail-biting convolutional code we use is small and , the additional complexity of the proposed scheme is less compared with the complexity of the conventional PCSPC decoder. Here, we adopt the parameter configurations in this paper to give a specific example. Assume that ,,, and ; then and are obtained by (11) and (12). Hence, compared to the complexity of the original PCSPC, the additional complexity of 3D polar code is about .

6. Conclusion

In this paper, 3D-PC is presented to lower the error floor of PCSPC. It makes the best use of the characteristics of parallel concatenation and serial concatenation. The simulation results verify the effectiveness of 3D-PC. In addition, EXIT chart is utilized to analyze the convergence threshold of 3D-PC under different permeability rate configurations. The obtained convergence thresholds can guide the choice of permeability rate of 3D-PC.

Conflicts of Interest

The authors declare that there are no conflicts of interest regarding the publication of this paper.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (no. 61771066), the National Natural Science Foundation of China (no. 61671080), and the National Science and Technology Major Project (no. 2017ZX03001004).

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