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| Energy-efficient techniques | Principle | Remarks |
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| Asynchronous design [22] | Voids clock synchronization in design | Could achieve less power than its synchronous equivalent [22] |
| Gate sizing | Reducing the gate size reduces its capacitance | May introduce delay |
| Adiabatic switching [23, 24] | Recovers clocking energy | Uses significantly less power than a conventional CMOS circuit [24]; relies on slow transition times |
| Transistor stacking [25] | Off-state transistors connected in series cause significantly less leakage than a single device. | Works in both active and standby mode |
| Subthreshold logic [26–28] | Utilizes subthreshold leakage current | Requires high-quality factor clocking and generally higher area; suffers degraded performance; suitable for low-activity application |
| Low-swing clocking [29, 30] | Reduces clock swing | Requires upsized clock buffers to maintain driving performance |
| Parallel computing [31–33] | Processors in parallel optimize energy. Pipelining exploits inherent parallelism in instructions to save power | Has been widely used to increase computational speed without increasing frequency, which increases dynamic power [34]. Pipelining, however, requires complex circuitry. |
| Logic in-memory architecture [35, 36] | In-memory logic for big-data applications | Mitigates the bottleneck in data exchange between logic and memory |
| Dual edge clocking [37] | Reduces the clock frequency to half of the single edge-triggered flip-flops | Could achieve the same performance with less power as single edge-triggered flip-flops at the cost of a larger area |
| Multithreshold voltage circuits [38] | Low threshold MOSFETs are used in critical paths, and high threshold MOSFETs are used in noncritical paths | Reduces leakage power |
| Power gating [39] | Chips are designed so that current to some blocks of the circuit that are in standby or sleep modes can be shut off | Reduces standby or leakage power |
| Adaptive body biasing | Adaptively switches the body-bias from a forward-bias to a reverse-bias condition when high performance is not needed | Reduces leakage power |
| Clock gating [40] | Adds logic to the circuit to prune the clock tree | Works to disable portions of the circuitry, saving switching power |
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