PackeX: Low-Power High-Performance Packet Classifier Using Memory on FPGAs

Table 1

Performance comparison of PackeX with the related work.

Packet classification engine	Platform	Memory/resource utilization	Power consumption (mW)	Throughput (Mpps)
Zhang et al.	FPGA	Maximum M/R utilization	1120	7 Mpps
Lakshminarayanan et al.	FPGA	Maximum M/R utilization	—	20 Mpps
Wang et al.	FPGA	Maximum M/R utilization	1200	—
Shen et al.	FPGA	Maximum M/R utilization	1900	—
Inayat et al.	FPGA	Average M/R utilization	33.72	20 Mpps
Ullah et al.	FPGA	Average M/R utilization	188	9 Mpps
Irfan et al.	FPGA	Average M/R utilization	—	33 Mpps
PackeX	FPGA	Minimum M/R utilization	17	119 Mpps