PackeX: Low-Power High-Performance Packet Classifier Using Memory on FPGAs

Table 3

Implementation results on Xilinx Virtex-7 FPGA for PackeX.

Approaches	No. of addresses/rules	Platform	No. of SRs	No. of LUTs	Throughput (Mpps)	Power (mW)
PackeX-I	64	Virtex-7	403	616	71	11
PackeX-II	128	Virtex-7	770	1095	119	17

Mpps: Mega packets per second; mW: milliWatt; SR: Slice Register; LUT: lookup table.