Abstract
The experimental results of the Fowler-Nordheim characterization using poly1-poly2 capacitors on CMOS ON Semi 0.5 μm technology are presented. This characterization allows the development, design, and characterization of a new current-mode analog nonvolatile memory. Experimental results of the memory cell architecture are presented and demonstrate the usefulness of the proposed architecture.
1. Introduction
For decades, the floating gate MOS transistors (FG-MOS) have been used as an important element for analog and digital circuit design. Over the years, a wide spectrum of floating gate devices has been proposed for analog applications. Some of them are related to the development of analog nonvolatile memories [1], where the storage of charge in a floating gate (FG) cell is later used as information in voltage-mode or current-mode. This kind of devices is very useful for trimming in analog circuits and information storage for artificial neural networks. Several methods have been used for injecting or removing charge onto a floating gate: the hot electron injection (HEI), Fowler-Nordheim tunneling (F-N) [2], and UV conductances [3]. Over the time, many analog nonvolatile cells have been proposed; Fujita and Amemiya [4] present a structure that has two floating gates connected through a high resistance ~1 GΩ. Though it is a compact cell, it is not achievable in standard CMOS processes, since the integration of such high resistances is not possible.
In the paper [5], Harrison et al. present an on-chip nonvolatile analog memory array. The design uses NMOS transistors with N-well layer as drain in order to address high voltages on chip. Thus, this high voltage is used to allow F-N for programming a specific cell in the whole array. However, the design of an NMOS with this feature violates a design rule related to “active to well edge” in standard CMOS technology.
Figueroa Toro [6] proposes a negative feedback floating gate configuration with two transistors, one capacitor and one inverter amplifier. In this case it is necessary to include an on-chip charge pump, which is used to induce the F-N mechanism. Hence, the design area is augmented by the need of special circuitry.
Moreover, Diorio et al. [7] presents a structure with two PMOS transistors. One transistor has a thin gate oxide that tunnels at much lower voltages. The other transistor uses high drain voltages to induce the HEI mechanism in order to increase the electron charge onto the floating gate. Nevertheless, the thin oxide layer tends to degrade with the use of the cell. Thus, the lifetime of the cell is reduced notably.
In this paper, the F-N characterization and the design of a current-mode analog nonvolatile memory are presented. The key element avoids the use of internal high voltages devices (>10 V) on-chip for addressing the F-N programming mechanism. The cell design uses a single floating gate, a poly1-poly2 injector, and a control gate. Thus, F-N tunneling is used to charge and discharge the floating gate. The sections of this paper are organized as follows: the next section will explain the characterization of the F-N current in poly1-poly2 capacitors. Section 3 gives an overview of the cell design. Section 4 reviews the simulations and the experimental results are presented. Finally, the conclusions are presented in Section 5.
2. F-N Characterization on Poly1-Poly2 Capacitors
Depending on the thickness of silicon oxide, there are several electron-transport mechanisms. The F-N tunneling is the dominant mechanism when the oxide thickness is greater than a few tens of nanometers and electrical fields () greater than 6 × 106 V/cm [2]. The current density () caused by the F-N tunneling through a SOS (silicon-oxide-silicon) capacitor of area can be described by the following classical equation: where is a constant, is the electrical field, is the effective electron mass in the oxide, is the electron charge, is the normalized Planck constant, and is the barrier height between conductor and isolator layer, in this particular case, highly doped polysilicon. As depicted in Figure 1, the - curves from 5 capacitors fabricated over 5 different chips are shown. When electrical field is less than 6.3 MV/cm, the current is negligible. Moreover, as electrical field increases, electrical current also increases; this suggests that F-N tunneling could be the dominant mechanism. To prove that the transport mechanism is F-N tunneling, it is necessary plot log (/) versus 1/ to obtain a straight line as shown in Figure 2.
The proposed floating gate transistor has a tunneling injector and a control gate (Figure 3). In this device, considering negligible parasitic capacitances, the floating gate potential (potential at FG node with respect to substrate) is approximately given by [8] where is the control gate voltage through capacitor; is the voltage at the charge injector that couples to the floating gate through capacitor , and is the total capacitance of the floating gate.
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(b)
For this case, the cell is designed with the condition ; thus, ratio . Hence, floating gate potential is practically defined by control gate potential ; that is, .
The F-N mechanism allows injecting or extracting electrons from the floating gate. As the potential difference between the floating gate and the charge injector is enough to achieve a critical electrical field, a current is established. The current density is theoretically characterized by the Fowler-Nordheim equation [2]: where is the current density, E is the electrical field in the oxide, and α and β are technological constants. For simplicity, we assume that charge injector-floating gate structure is a parallel plate capacitor of area separated by a distance . Thus, the electric field in the injector is given by where . Considering that current tunneling is achieved through all the charge injector area, we can express (3) as follows: where α and β are fit parameters which must be extracted experimentally from CMOS technology.
In order to obtain α and β from experimental data, (5) must be linearized. Therefore, using natural logarithm in both sides, (5) is transformed to This has the linear form where Thus, through the I-V characterization of poly1-poly2 injector, α and β can be extracted using linear fitting.
2.1. Parameter Extraction
Several testing poly1-poly2 capacitors were designed and fabricated on CMOS 0.5 μm technology; these capacitors have an area A = 180 μm 210 μm and d = 38.4 nm (Figure 4). The I-V curves from 40 capacitors were obtained using Keithley 2400 sourcemeters. The extracting methodology was accomplished with the arithmetic average of the I-V curves. The following values for A/V2 and β = 150.56 MV/cm were obtained; consequently, the F-N current expression is This expression brings a close approximation for the F-N current for a given poly1-poly2 tunneling injector with area and distance between plates.
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Only five I-V curves from different capacitors are shown for clarity in Figure 5; the average curve and the model for the capacitors are also shown in the same plot. A good fitting among I-V measurements, average, and the proposed model can be noticed.
3. Memory Cell Design
The current-mode analog memory cell proposed in this paper stores charge onto the floating gate of MFG1 and MFG2 transistors in order to set a given current and , (Figure 6). This current is stored permanently and results from the copy of an input current by using a feedback loop. Thus, the stored charge can be read out as an analogue current from MFG2. Some important electrical characteristics of the cell are presented in Table 1.
The operation of the storage cell is explained in three stages as follows.
3.1. Initialization
The capacitor is set to an initial potential of = −25 V and transistor M12 must be turned on in order to lead to ground. This condition = 0 V sets = 0 V through capacitor . As a result, = −25 V enabling F-N tunneling current through poly1-poly2 capacitor . Consequently, electrons are injected to the FG causing a potential drop of relative to ground, increasing the current from MFG1 transistor. This memory has been verified to store analogue current values in the range of 30 μA < < 70 μA; therefore, the initial current condition must fulfill > 70 μA for a proper operation of the cell feedback loop.
3.2. Programming
The programming stage starts setting an input current value , which will be stored in the cell permanently. A potential of = 25 V must be also established on and transistor M12 must be turned off. The current to be stored is introduced by the current source , where transistors M1, M2, and M3 act as a cascode current mirror with high output impedance at node “x.” Thus, node “x” will have high gain and since > , the potential in this node will be close to . The comparator allows even a higher gain from node “x” and was considered in order to reduce the error of /. Moreover, this comparator allows an adjustable reference through . The push-pull inverter brings a rail-to-rail output from the comparator output; indeed, this inverter has a = 8 V whose output is induced to the FG through capacitor .
Thus, when voltage at node “x” is close to , the inverter brings = 0 V which sets the FG also to 0 V, as mentioned above. This voltage difference between and is greater than 24 V ( > 24 V); then, electron tunneling is achieved, which extracts electrons from the FG causing an increase on . As a result, the current is decreased. Consequently, potential rises until node “x” reaches ≈ by the use of the feedback loop. When is slightly greater than , the potential at node “x” drops to a value near ground; this causes a “high” output from the inverter, = 8 V. This 8 V output of the circuit applied to capacitor stops tunneling since now < 24 V. This control loop makes this cell a novel design since only 8 V on-chip is necessary in order to stop tunneling with the feedback loop.
Finally, current of MFG transistor will be equal to current, which is permanently stored by means of the stored charge in the FG.
3.3. Reading
Cell reading is performed under the following conditions: = 0 V and = 0 V. For this purpose, transistor M12 must be turned on in order to lead to ground. The output current is a copy of and is obtained from the drain of transistor M4.
4. PSpice Simulations and Experimental Results
4.1. Macromodel for Electrical Simulation
Spice is a world standard program for electrical circuit simulation. A macromodel is a combination of Spice models used for a special purpose device. Since F-N tunneling current is not modeled in Spice, the F-N expression is implemented as a macromodel with the use of a voltage-controlled current source (VCCS); that is, where “G” is associated with a voltage controlled current source and 1 and 2 are the nodes where the current source is connected. Node 1 represents external applied voltage which is ground referenced and node 2 represents the . The “VALUE” parameter allows the implementation of (9) including the injector area of ; in this case A = 1.8 μm × 1.8 μm and distance d = 38.4 nm. Additionally, a resistor R1 is included with a high value in order to improve simulation convergence. The VCCS G1 and R1 are shown in dashed line in Figure 6.
4.2. Spice Electrical Cell Simulation
An electrical cell simulation using PSpice is shown in Figure 7. The cell also includes resistor R2, which is used for improving convergence and helps the simulator to set the DC operation point at the floating gate. Furthermore, capacitor models the FG-substrate parasitic capacitor. In this case this capacitor can be calculated using the layer capacitance parameters given by the foundry and the injector area, in this case, has a value of = 360 fF. When an input current = 70 μA is established on the cell, the initial output current is = 160 μA and after 40 s this output current drops to ~70 μA. At this point, rises to 8 V and F-N tunneling is stopped. Afterwards, at 50 s, the is removed and transistor M14 is turned on; this enables the readout current, = 70.1 μA. The cell worked properly at the range 70 μA < < 30 μA. The highest error, error = , is obtained when current values are near 30 μA. It is important to notice that although a deviation in (9) could be present, only the cell convergence time to reach would be affected by several seconds. A microphotograph of a chip is shown in Figure 8.
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The measured relative error percentages for several programming input current values are shown in Figure 9. The error calculation was considered using From experimental data, the error is less than 5% in the range 70 μA < < 50 μA. Therefore this is considered the working range of the cell. In Figure 10, the plot shows a set of five cells supplying currents between = 60 μA to 65 μA over a long period of time. The charge retention of the floating gate has been confirmed by the measurements of the cells over 1000 minutes. In submicron technologies, gate leakage is well known [9]; thus, a constant measurement of the cell could show a change in the charge trend. Nevertheless, a further statistical analysis of this situation should be considered for periods ≫ 1000 min, since this could give important information about the usefulness of the cell, that is, reliability and refreshing cycles.
In Figure 11, the graph shows ambient temperature measurement at the same time span. A correlational fluctuation of the current value is observed and caused by the ambient temperature. Considering Δ from Figure 10 and ΔT from Figure 11, the storage cell presents a temperature dependence of −221 nA/°C. Therefore, the stored charge onto the floating gate does not present a significant change at the same period of time.
5. Conclusions
In this work, a novel nonvolatile current-mode analog memory cell architecture is presented. A control loop is used with only 8V to stop F-N tunneling. This is a new approach that allows the use of standard circuitry internally in order to program nonvolatile analog cells on chip. Experimental results show that the cell presents a useful range of values with a maximum error of 5%. The functionality of the cell was analyzed through a long period of time (1000 min) and also temperature performance was analyzed.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.