Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

Table 2

Comparison of various carry select adders.

Adder	Total power (W)	Delay (ns)	Power-delay product (10^−15)
8-bit regular; CSLA	203.9	1.719	350.5
8-bit modified; CSLA [10]	188.4	1.958	368.5
8-bit CSLA; [14]	187.58	1.976	370.8
8-bit CSA using reversible logic [15]	180	17.2	3096
8-bit proposed; CSLA	147.4	2.18	321.3