Research Article  Open Access
Design of Low Power and Efficient Carry Select Adder Using 3T XOR Gate
Abstract
In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3T XOR gate is used to design an 8bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as powerdelay product (PDP) as compared to regular CSLA and modified CSLA.
1. Introduction
In today’s VLSI circuit designs, there is a significant increase in the power consumption due to the increasing speed and complexity of the circuits. As the demand for portable equipment like laptops and cellular phones is increasing rapidly, great attention has been focused on power efficient circuit designs [1–4]. Adders are the basic building blocks of the complex arithmetic circuits. Adders are widely used in Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), and floating point units, for address generation in case of cache or memory access and in digital signal processing [5–7].
Having adders with fast addition operation and low power along with low area consumption is still a challenging issue. Depending upon the area, delay, and power consumption, the various adders are categorized as ripple carry adder (RCA), carry select adder (CSLA), and carry lookahead adder (CLAA). CSLA provides a compromise between the large area with small delay of CLAA and small area but longer delay of RCA [8]. CSLA uses pair of RCAs for addition, that is, one block of RCA with (carry in) = 0 and other block of RCA with = 1. Depending on the value of previous carry, the final sum and carry outputs are selected using multiplexer. Due to the pair of RCAs used for each bit addition, the simplest kind of CSLA is not very efficient [9].
Keeping in mind that XOR gates are the building blocks of adders, here in this work, we use a 3TXOR gate to design an 8bit CSLA. The main advantage of using 3TXOR gate is that the power consumption of the circuit decreases due to the large decrease in number of switching transistors (MOSFETs) used in the design of 8bit CSLA.
This paper is organized as follows. Section 2 presents the earlier works on carry select adder including the detailed structure of regular CSLA as well as modified CSLA. Section 3 explains the proposed CSLA and evaluates the reduction in switching transistors (MOSFETs) count. The implementation details as well as simulation results of proposed CSLA are analyzed in Section 4 and Section 5 concludes the whole work.
2. Earlier Works on Carry Select Adder
In digital adders, the speed of addition is limited due to the time taken by the carry signal to propagate through the adder. The regular carry select adder (RCSLA) was introduced to mitigate the problem of carry propagation delay by independently generating multiple carries and then selecting the correct sum and carry outputs depending on the value of previous carry [9]. As previously discussed, this type of CSLA (i.e., RCSLA) was not area efficient due to the use of pair of RCAs (each for and ) to produce the final sum and carry output. The 8bit RCSLA is shown in Figure 1.
To make low power consumption and an area efficient CSLA, an addone circuit known as Binary to Excess1 Converter (BEC) circuit was introduced. This BEC circuit replaced the RCA with used in RCSLA as lesser numbers of logic gates were used in BEC as compared to bit RCA [10–12]. The truth table and circuit diagram of 4bit BEC are shown in Figure 2 and Table 1, respectively.

The 8bit modified carry select adder (MCSLA) using BEC is shown in Figure 3. As shown in the Figure 3, 8bit MCSLA was divided into four groups with different bit sizes of RCA and BEC. MCSLA consists of RCAs (for ), BEC circuits (for ), and multiplexers (MUX). One input to the MUX is sum along with carry outputs from RCA and another input to the MUX is sum along with carry outputs from BEC circuit. The final sum and carry outputs are selected depending upon the value of previous carry which is inputted as the select line to the MUX [10].
3. Proposed Work on CSLA
In this work, we use a modified XOR gate as it forms the basic building block of CSLA. Here, we use a 3T XOR gate instead of 12T XOR gate used in previous designs of RCSLA and MCSLA which helps in more efficient design of 8bit CSLA [13]. The circuit diagrams of 3T XOR gate and proposed 8bit CSLA are shown in Figures 4 and 5, respectively.
The overall performance of CSLA in terms of power consumption, transistor count, and powerdelay product (PDP) can be enhanced by modifying the XOR gate. A single modified XOR gate (3T XOR gate) used in this work has 9 lesser transistors as compared to the XOR gate (12T XOR gate) used in earlier works on CSLA. The proposed 8bit CSLA is divided into 4 groups as shown in Figure 5.
The total reduction in transistor count for each group is calculated below.
Group 1. It contains one full adder. Each full adder consists of two XOR gates. Therefore total transistor count reduction for group 1 is number of XOR gates used = 2; transistor count reduction = 18 ().
Group 2. It contains one full adder, one half adder, and one 3bit Binary to Excess1 Converter (BEC). The transistor count reduction for group 2 is as follows: number of XOR gates used = 5 (); transistor count reduction = 45 ().
Group 3. It contains one full adder, one half adder, and one 3bit Binary to Excess1 Converter (BEC). The transistor count reduction for group 2 is as follows: number of XOR gates used = 5 (); transistor count reduction = 45 ().
Group 4. It contains two full adders, one half adder, and one 4bit BEC. The transistor count reduction for group 4 is as follows: number of XOR gates used = 8 ; transistor count reduction = 72 ().Therefore the overall reduction in number of switching transistors (MOSFERTs) in proposed 8bit CSLA as compared to the previously designed 8bit MCSLA is 180. Hence, the reduction in number of switching transistors reduces the power consumption as well as the powerdelay product (PDP) of 8bit CSLA.
4. Simulation Results
The proposed 8bit CSLA has been successfully tested and synthesized in Tanner Tools using 90 nm technology with a supply voltage of 1.0 V. The power consumption and delay time of proposed 8bit CSLA are calculated for all input conditions and the worst case power consumption as well as delay time is noted down. The power consumption, delay time, and powerdelay product (PDP) of proposed 8bit CSLA are compared with 8bit RCSLA and MCSLA. The results of proposed 8bit CSLA are also compared with the 8bit CSA proposed in recent studies [14, 15]. The comparison is shown in Table 2.
It is clear from Table 2 that power consumption of proposed 8bit CSLA is reduced by 27.7% and 21.7% when compared with RCSLA and MCSLA, respectively. The powerdelay product (PDP) shows a similar trend as PDP is reduced by 8.3% and 12.8% when compared with RCSLA and MCSLA, respectively. Compared with the reversible logic style based 8bit CSA [15], the proposed design has 18.1% reduction in power consumption and 89.6% reduction in PDP. Compared with the CSLA [14], the proposed CSLA has 21.7% reduction in power consumption and 13.3% reduction in PDP.
The postsimulation inputoutput waveforms for the 8bit proposed CSLA are shown in Figures 6 and 7, respectively. The proposed design is simulated with a 12.5 MHz waveform with rise and fall times of 4 ns.
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Figure 8 shows the comparison of various carry select adders in graphical form for the data given in Table 2. We can see from the graph that the proposed CSLA has minimum powerdelay product (PDP) as well as the minimum power consumption when compared with regular CSLA, modified CSLA [10], CSLA [14], and reversible logic style based 8bit CSA [15].
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5. Conclusion
A simple approach of enhancing the performance of XOR gate to design an 8bit CSLA is used in this paper. The proposed CSLA has large decrease in switching transistors (MOSFETs) due to the use of 3T XOR gate. On comparing this proposed 8bit CSLA with other existing 8bit CSLAs like RCSLA and MCSLA, there is 27.7% and 21.7% reduction in power, respectively. The powerdelay product (PDP) is also reduced by 8.3% and 12.8% when compared with RCSLA and MCSLA, respectively. The proposed 8bit CSLA has the best performance compared with other 8bit CSLAs present in literature. It would be interesting to design 16bit CSLA and 32bit CSLA using 3T XOR gate.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
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Copyright
Copyright © 2014 Gagandeep Singh and Chakshu Goel. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.