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Advances in Materials Science and Engineering
Volume 2013, Article ID 905686, 7 pages
Research Article

A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology

1Department of Electronics Engineering, Chien Hsin University of Science and Technology, No. 229 Chien Hsin Road, Zhongli, Taoyuan 320, Taiwan
2Department of Electronic Engineering, Ming Chuan University, No. 5 De Ming Road, GuiShan, Taoyuan 333, Taiwan

Received 1 October 2013; Accepted 2 November 2013

Academic Editor: Tung-Ming Pan

Copyright © 2013 Chih-Yao Huang and Fu-Chien Chiu. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case.