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Advances in Materials Science and Engineering
Volume 2014 (2014), Article ID 196732, 5 pages
Research Article

Design and Simulated Characteristics of Nanosized InSb Based Heterostructure Devices

1Department of ECE, Annai Vailankanni College of Engineering, Tamil nadu, India
2Department of IT, RMK College of Engineering and Technology, Chennai, India
3Centre for Information Technology and Engineering, Manonmaniam Sundaranar University, Tirunelveli, India
4Department of ECE, Shri Sapthagiri Institute of Technology, Vellore, India

Received 27 June 2014; Revised 10 August 2014; Accepted 11 August 2014; Published 8 September 2014

Academic Editor: George Z. Kyzas

Copyright © 2014 T. D. Subash et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Indium antimonide nanoparticles were synthesized at room temperature. X-ray diffraction measurements are utilized to characterize the nanocomposites. The InSb nanoparticle has an average particle size in a range of 47 mm to 99 mm which is observed using the XRD result. The InSb is a material which is used to design the transistor. For designing purpose the simulator TCAD is used, by which the HEMT device is structured and its performance is analyzed and it is found that transistor operates as normal devices. This designed device is more valuable since a nanocomposite InSb material is used as a channel in HEMT device, thereby leading to the nanosized HEMT device. In addition, InSb has the property of high saturation velocity and mobility which results in higher performance of the device than any other materials in III-V compounds.

1. Introduction

For the last 30 years, Moore’s law has been a guiding principle for the semiconductor industry. Sustaining Moore’s law requires continuous scaling of Si MOSFETs. The physical gate length of Si-transistors that are utilized in the current 65-nm node is about 30 nm [15]. It is expected that this critical dimension will reach about 10 nm in 2015. While a matter of considerable debate, it is widely believed that this is the ultimate limit of CMOS scaling. With this prospect, identifying a new semiconductor logic device technology that can sustain Moore’s law for a few additional generations is becoming increasingly pressing [615]. Often mentioned candidates are carbon-nanotube transistors, semiconductor nanowires, and, further out, spintronics. However, these device concepts are hardly outside the prototyping stage. The binary compound semiconductors AlSb, GaSb, InSb, and InAs along with their related alloys are candidates for high-speed, low-power electronic devices [16]. Applications could include high-speed analog and digital systems used for data processing, communications, imaging, and sensing, particularly in portable equipment such as hand held devices and satellites [17]. The development of InSb based transistor for use in low-noise high-frequency amplifiers, digital circuits, and mixed signal circuits could provide the enabling technology needed to address these rapidly expanding needs.

The first HEMT were fabricated with GaAs channels and AlGaAs barriers [18]. These devices are also known as modulation doped field effect transistor (MODFET). In order to achieve higher electron mobility and velocity indium was added to the channel. In order to improve further additional indium was added to the channel and the barrier material was changed to InAlAs. The logical progression of this trend is to use pure InAs as channel along with the nearly lattice-matched Alsb and AlGaSb for the confining layers as arsenide’s are not suitable barriers. For the past 20 years it has demonstrated the best high frequency performance of any transistor technology as measured by cutoff frequency. Current world record is 562 GHZ and InGaAs HEMT manufacturing technology is matured.

This paper deals with the preparation procedure of indium antimonide nanoparticle in lab. The characteristics of the prepared nanoparticle are analyzed. The HEMT device is designed using TCAD software by using nanosized InSb particle as channel. The characteristics of nanoparticle are observed using XRD image and the performance of transistor is analyzed using simulator. This is dealt in the section “result and discussion”.

2. Experimental Procedure of Indium Antimonide

One hundred and fifty millilitres of polyethylene glycol should be taken in a beaker. Dissolve stoichiometric amount of indium trichloride (InCl3) and antimony trichloride (SbCl3) in polyethylene glycol at room temperature. Zinc powder was gradually added to the solution. Leave the solution to be stirred for about 2-3 hours. The process should be continued till InSb was precipitated and turned it into grey colour. Keep the solution to be stirred well for half an hour and then it must be aged in the mother liquor for a day at a temperature of 25°C. After completion of this period, the precipitate was centrifuged and washed several times with distilled water. The precipitate was dried in hot oven at 120°C for an hour and kept in water bath for 2 hours. The resultant particle is grinded well to obtain fine indium antimonide nanoparticle.

The chemical reactions are as follows:

3. Design of HEMT Device

The cross-sectional schematic view of our InSb HEMTs is shown in Figure 1. The layer structure was grown on semi-insulating GaAs substrates followed by 300-nm Al0.52In0.48Sb buffer layer, 5 nm of InSb channel, 1-nm GaAs barrier layer, and a 20-nm InSb cap layer. All the layers were designed to be undoped, except for the top InSb layer, which is a heavily doped N+ layer intended for the source and drain regions of the HEMT. Mobility of electrons (78000 cm2/(V*s)) in 2DEG for InSb is higher than Silicon. Mobility was improved with a slight increase of 2DEG. Thickness of the barrier layer affects 2DEG concentration and vertical gate field which controls gate leakage current and breakdown and can also affect device degradation. The ohmic contact of titanium/gold is developed as source and drain. Ni/Au is used as gate layer.

Figure 1: Cross-sectional schematic view of InSb/AlInSb HEMTs.

The prepared InSb nanoparticle is used as a channel in the transistor. The transistor is designed using TCAD software and analysed the performance. In our novel research work the synthesis of InSb nanoparticle is highlighted in previous session since this is used as a layer for designing heterostructure devices. InSb is an III-V compound material. InSb is used in the channel since it is a narrow-gap semiconductor with an energy band gap of 0.17 eV at 300 K and 0.23 eV at 80 K. There will be a strong carrier confinement in the channel at the heterointerface. It reduces off-state leakage current. Degradation of mobility decreases due to the interface states as layers are lattice matched. The most important property of the material is high saturation velocity which results in higher operating frequency.

3.1. Current-Voltage, Noise Figure, and Temperature Characteristics Analysis

The saturation current is the drain current at  V. The leakage current is the drain current at  V and  V. The transconductance is extracted from the slop of at 1 V. is the threshold voltage of the HEMT given by where is Schottky gate effective barrier height of the is the discontinuity of the conduction band at the interface between the UID-InSb and the AlInSb layers.

is the doping concentration in -AlInSb layer, and σ is the polarization induced charge density at the interface.

The minimum noise figure and the minimum noise temperature are then defined as

4. Results and Discussion

4.1. Characterization of Powder

The samples of Insb were synthesized to investigate the crystalline phase. Figure 2 shows the XRD result. The samples were scanned in 2θ range from 0° to 180°. The size of InSb was estimated by the peaks of XRD image. With the help of peaks the size of the crystal was calculated.

Figure 2: XRD pattern of InSb sample.

The standard Scherrer equation is used to find the particle size. The equation is given as The wavelength is lamda 0.154060 nm, is the peak position, and is the full peak width at half of the maximum intensity. Using this, the particle size is found to be in the range of 47 nm to 99 nm.

4.2. Transistor Characteristics

The - characteristics of the device is simulated by keeping gate voltage as constant for to 10 V and 0–20 V as shown in Figures 3 and 4. This is performed to study the switching characteristics of transistor. When  V, knee voltage is 5.8 V. Thus state will be switched into state and vice versa. This replicates that the device works as normal transistor.

Figure 3: Simulated HEMT output characteristics ( versus ) for between 0 V and 10 V and various .
Figure 4: Simulated HEMT output characteristics ( versus ) for between 0 V and 20 V and various .

Figures 5 and 6 show the saturation current and leakage current as a function of gate voltage. As gate voltage increases saturation current increases although leakage current also increases. This is mainly due to the threshold voltage.

Figure 5: Variation of for HEMT at fixed channel length.
Figure 6: Variation of for HEMT at fixed channel length.

For low drain source voltage values, that is, 0-1 V, in the channel region the gate bias induces an accumulation of electrons. This causes a reduced channel resistance. Hence the channel width is decreased which in turn increases the electric field across the channel junction.

From Figure 7, it is observed that for low values of gate voltage, minimum noise figure is higher for higher value of noise temperature constant . This occurs due to higher value of drain noise current and gate noise current for higher values of which in turn lead to higher values of , , and noise coefficients. However, for higher values of gate voltage, increasing leads to decrease in the gate noise current and hence decrease in the gate noise coefficient . Due to this is observed to decrease with increase in at higher drain current.

Figure 7: Minimum noise figure gate voltage.

The impact of noise temperature constant and diffusion coefficient on minimum noise temperature is illustrated in Figure 8. From the figure it is observed that increases with increase in at low values of gate voltage. This is attributed to higher value of thermal noise induced drain noise current and gate noise current which lead to higher value of , , and noise coefficients. This in turn results in higher and hence higher with increase in noise temperature constant at low values of drain current. However, at higher values of drain current, is observed to decrease with increase in which is attributed to the decrease in gate noise current which results in lower value of .

Figure 8: Minimum noise temperature gate voltage.

5. Conclusion

In this paper, nanocrystalline indium antimonide power of 47–99 nm is synthesized by chemical process. The obtained nanoparticle is in the range of 47 to 99 nm which is analysed using XRD. This particle is used as a channel in transistor design. The transistor is designed using TCAD. The scope of this nanoparticle is in the design of HEMT device to limit gate voltage, leakage current, and short channel effects.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.


  1. G. Ira and V. Mehrotra, “Synthesis of magnetic, dielectric or phosphorescent NANO composites,” U.S. Patent 7,431,862, 2008. View at Google Scholar
  2. T. Chiang, “A novel short-channel model for threshold voltage of trigate MOSFETs with localized trapped charges,” IEEE Transactions on Device and Materials Reliability, vol. 12, no. 2, pp. 311–316, 2012. View at Publisher · View at Google Scholar · View at Scopus
  3. R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, Wiley-IEEE, 3rd edition, 2010.
  4. W. S. Lau, L. Zhong, A. Lee et al., “Detection of defect states responsible for leakage current in ultrathin tantalum pentoxide (Ta2O5) films by zero-bias thermally stimulated current spectroscopy,” Applied Physics Letters, vol. 71, no. 4, pp. 500–502, 1997. View at Publisher · View at Google Scholar · View at Scopus
  5. K. Roy and K. S. Yeo, Low Voltage, Low Power VLSI Subsystems, McGraw-Hill Professional, 2004.
  6. K. Ko, J. Seo, D. Kim et al., “The growth of a low defect InAs HEMT structure on Si by using an AlGaSb buffer layer containing InSb quantum dots for dislocation termination,” Nanotechnology, vol. 20, no. 22, Article ID 225201, 2009. View at Publisher · View at Google Scholar · View at Scopus
  7. H. Uchiyama, T. Taniguchi, and M. Kudo, “Suppression of plasma-induced fluorine damage in P-HEMTs using strained InSb barrier,” IEICE Electronics Express, vol. 1, no. 16, pp. 513–517, 2004. View at Publisher · View at Google Scholar
  8. K. Takei, S. Chuang, H. Fang et al., “Benchmarking the performance of ultrathin body InAs-on-insulator transistors as a function of body thickness,” Applied Physics Letters, vol. 99, no. 10, Article ID 103507, 2011. View at Publisher · View at Google Scholar · View at Scopus
  9. S. T. Myers, J. E. Baker, A. C. S. Readhead, E. M. Leitch, and T. Herbig, “Measurements of the sunyaev-zeldovich effect in the nearby clusters A478, A2142, and A2256,” Astrophysical Journal Letters, vol. 485, no. 1, pp. 1–21, 1997. View at Publisher · View at Google Scholar · View at Scopus
  10. M. Levinshtein, M. S. Michael, and S. Rumyanstev, Handbook Series on Semiconductor Parameters, vol. 2, World Scientific, Singapore, 1996.
  11. C. Hilsum, “Simple empirical relationship between mobility and carrier concentration,” Electronics Letters, vol. 10, no. 13, pp. 259–260, 1974. View at Google Scholar · View at Scopus
  12. S. Liu, Z. Dai, H. Chen, and H. Ju, “Immobilization of hemoglobin on zirconium dioxide nanoparticles for preparation of a novel hydrogen peroxide biosensor,” Biosensors and Bioelectronics, vol. 19, no. 9, pp. 963–969, 2004. View at Publisher · View at Google Scholar · View at Scopus
  13. H. Zhou, R. Tian, M. Ye et al., “Highly specific enrichment of phosphopeptides by zirconium dioxide nanoparticles for phosphoproteome analysis,” Electrophoresis, vol. 28, no. 13, pp. 2201–2215, 2007. View at Publisher · View at Google Scholar · View at Scopus
  14. K. Kumar and S. Jabaraj, “Nand gate using FinFET for nanoscale technology,” Journal of Engineering Science and Technology, vol. 2, no. 5, pp. 1351–1358, 2010. View at Google Scholar
  15. J. Conde, A. Cerdeira, M. Pavanello, V. Kilchytska, and D. Flandre, “3D simulation of triple-gate MOSFETs with different mobility regions,” Microelectronic Engineering, vol. 88, no. 7, pp. 1633–1636, 2011. View at Publisher · View at Google Scholar · View at Scopus
  16. C. S. S. R. Kumar, M. Aghasyan, H. Modrow et al., “Synthesis and characterization of S-Au interaction in gold nanoparticle bound polymeric beads,” Journal of Nanoparticle Research, vol. 6, no. 4, pp. 369–376, 2004. View at Publisher · View at Google Scholar · View at Scopus
  17. D.-H. Kim and J. A. del Alamo, “Beyond CMOS: logic suitability of In0.7Ga0.3As HEMT,” in Proceedings of the International Conference on Compound Semiconductor Manufacturing Technology (CS MANTECH '06), pp. 251–254, Vancouver, BC, Canada, April 2006.
  18. D.-H. Kim, J. A. del Alamo, J.-H. Lee, and K.-S. Seo, “Performance evaluation of 50 nm In/sub 0.7/Ga/sub 0.3/As HEMTs for beyond-CMOS logic applications,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '05), pp. 767–770, Washington, DC, USA, 2005.