An Analytical Gate-All-Around MOSFET Model for Circuit Simulation
A generic charge-based compact model for undoped (lightly doped) quadruple-gate (QG) and cylindrical-gate MOSFETs using Verilog-A is developed. This model is based on the exact solution of Poisson’s equation with scale length. The fundamental DC and charging currents of QG MOSFETs are physically and analytically calculated. In addition, as the Verilog-A modeling is portable for different circuit simulators, the modeling scheme provides a useful tool for circuit designers.
According to Moore’s law, CMOS transistors continue to scale. The transistor size scaling provides for increased packing density, improves circuit speed, and lowers power consumption. However, many small-geometry effects have surfaced such as short-channel effects, limiting the device performance. In order to overcome these issues, improving device gate controllability is necessary. Multigate transistor architecture is regarded as one of the most effective ways to improve the short-channel effects and to enhance the gate controllability [1–3]. The gate-all-around (GAA) MOSFETs have drawn much attention for ultimate device scaling. To expedite further VLSI development using GAA devices, we use Verilog-A to develop the SPICE device model which can be used by circuit/device designers with a simple set of physical parameters.
2. Potential Model and I-V Model Based on Scale Length
We propose a scale-length based GAA MOSFET model. The schematic diagram of the QG MOSFET for modeling is shown in Figure 1. The model is based on an undoped n-channel multigate MOSFET.
Unlike most models limited to a certain specific type of the gate, the proposed model is highly scalable and is generic to both quadruple-gate (QG) and cylindrical-gate structures. Poisson’s equation for potential can be written as where is the channel doping (assumed to be uniform in the model) and represents any position in the channel , which is equivalent to for any specific location in plane . The solution for iswhere , , and is the channel center potential, which can be solved at aswhere is defined as the scale length:The scale length gives a measure of the short-channel effects inherent in a device structure. To ensure our model accuracy, we use TCAD simulation for calibration. Figure 2 shows the calibration flow for SPICE model parameters. Due to the physical nature of the model, the calibration process is straightforward. To demonstrate the predictability of the model, it is applied to a case with model parameters nm, nm, nm, and nm. Figure 3 shows the predicted I-V characteristics where near ideal subthreshold slope and drain-induced barrier lowering (DIBL) of 79.68 mV/V are predicted.
3. Charge Model
The terminal charges are based on previous potential equation. The boundary conditions used for (1) are for and for , where is the oxide capacitance, is the flat band voltage, is the surface potential, is the surface electric field, and is silicon charge density per unit gate area [6, 7]. From them, we can obtain the mobile charge density as a function of the difference between surface and center potentials :where is the fixed charge density, is the quasi-Fermi potential in the channel, and is the Fermi potential. takes the value of at the source and at the drain . Figure 4 shows the charge density (per unit area) at the source end in logarithmic and linear scale.
We then use and to calculate charge current aswhere is short-channel effect mobility, is the channel width, is the subthreshold slope degradation, and is the channel length modulation.
Figure 5 shows the charging current network. Based on the charging current network, we can obtain total inversion capacitance by measuring gate charging current from AC simulation, as shown in Figure 6.
4. VLSI Application
To ensure the validity of the model for IC simulation, different types of circuit simulation including inverters and static random access memory (SRAM) are used for verification . Inverters are the basic circuit block for assessing CMOS technology. Figures 7 and 8 show the inverter DC and transient simulation using the GAA model, from which the intrinsic inverter speed can be extracted. The circuit simulation gives an insight to device performance very efficiently based on the physical DC I-V and charge models.
Figure 9 shows the circuit schematic of a 6-T SRAM. To analyze the hold static noise margin (SNM), the bit line (BL) and bit line bar (BLB) are biased at a high voltage (usually ) and word line (WL) is biased at low voltage. One may measure the difference in voltage between point Q and point QB. Because the word line is in the low voltage condition, the two pass-gate transistors on the sides are kept at off condition. The potential changes in BL and BLB do not influence the potentials at point Q and point QB. When analyzing the read static noise margin, a high voltage was given to WL to keep two transistors on two sides on. The BL and the BLB are also biased at a high voltage. One can measure the difference in voltage between point Q and point QB. An example of read and hold SNMs is shown in Figure 10 .
Figure 11 shows the simulated static noise margin of the 6-T SRAM using the proposed GAA model. In the hold mode, two transistors on two sides are off, so the inputs in BL and BLB do not influence the potentials at point Q and point QB. Such SNM reflects the ideal voltage transfer characteristics of the inverter. However, in the read mode, two transistors on the sides conduct, so BL and BLB will influence the conditions at point Q and point QB. As can be seen, the read SNM region is much smaller than that of the read SNM region.
A generic and charge-based compact modeling approach applicable to both quadruple-gate and cylindrical-gate structures was proposed. The model can be used straightforwardly with physical parameters such as gate work function and structural parameters. The model is analytical and efficient enough for circuit applications.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
The authors are grateful to the National Chip Implementation Center and National Center for High-Performance Computing for computational facilities. This work is supported in part by the Ministry of Science and Technology of Taiwan.
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