Table of Contents Author Guidelines Submit a Manuscript
ElectroComponent Science and Technology
Volume 8, Issue 1-2, Pages 91-98

Multi-Layer 2 Mil Line Technology

Toshiba R&D Centre, Toshiba Corporation, Japan

Copyright © 1981 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Multi-layer 2 mil line technology has been increasingly required for VLSI and very high speed logic devices. This technology makes it possible to shorten the length of interconnection lines between VLSI silicon chips. Thus the signal propagation delay on the transmission lines can be minimized.

Multi-layer 2 mil line technology research history, the new method and usages are discussed in this paper.