A 0.8–6 GHz Wideband Receiver Front-End for Software-Defined Radio

Table 1

Summary of the implemented and recently reported state-of-the-art CMOS wideband and tunable-band receiver front-ends.

	Frequency (GHz)	𝑆11 (dB)	Conversion gain (dB)	Noise figure (dB)	IIP3 (dBm)	Supply voltage (V)	Power (mW)	Area (mm^2)	Technology
This work	0.8~6	<−7.3	17~20*	4.5~5.9	−10~−5	1	13*	0.48*	90 nm CMOS
[2] 2008 ISSCC	0.6~10	<−10	14*	7	0	1.2	30*	1*	45 nm CMOS
[3] 2007 ISSCC	2~8	−8	23*	4.5	−7	1.2	27.8*	0.48*	65 nm CMOS
[4] 2006 JSSC	0.8~6	N/A	18~20^#	5~5.5	−3.5	2.5	28.5*	3.8^$	90 nm CMOS
[5] 2012 TMTT	0.6~3	<−8	42~48^$	3	−14	1.2	30^$	1.5^$	130 nm CMOS
[6] 2011 RFIC	0.1~3	N/A	33~55^$	3.5~6	N/A	1.2	14.5~48.5^$	2.2^$	130 nm CMOS
[7] 2009 JSSC	0.1~5	N/A	−2~82^$	2.3~6.5	−10~−3	1.1	59~115^$	2^$	45 nm CMOS
[8] 2008 MWCL	3~5	<−7.6	19.8~24.6*	15.4~17.4	>−6	2	16*	1.14*	0.18 um CMOS
[9] 2006 ISSCC	3~8	N/A	15~21*	5~6.5	−2.6	2.3	44.9*	0.35^*@	0.18 um CMOS

∗Front-end; ^#LNA only; ^$Whole receiver; ^@active area only.