CMOS Realization of All-Positive Pinched Hysteresis Loops

<div>Simulated <svg height="13.9769pt" id="M405" style="vertical-align:-5.341001pt" version="1.1" viewbox="-0.0498162 -8.6359 34.0501 13.9769" width="34.0501pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M244 607C244 633 228 655 200 655C166 655 146 618 146 594C146 564 166 546 191 546C221 546 244 574 244 607ZM222 91L209 114C184 94 148 66 133 66C127 66 124 73 130 96L201 370C213 416 211 448 191 448C162 448 88 407 29 352L42 328C73 354 104 371 114 371C120 371 119 365 115 345L53 92C32 5 45 -12 68 -12C103 -12 186 50 222 91Z" id="g113-106"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="273" vert-adv-y="273" xpluscharwidth="3.549"></glyph.data></g><g transform="matrix(.0091,0,0,-0.0091,3.484,3.132)"><path d="M138 535C169 535 191 560 191 589C191 620 168 644 139 644S85 620 85 589C85 560 110 535 138 535ZM257 0V30C192 35 185 43 185 109V453C142 435 94 422 40 414V386C101 378 104 372 104 311V109C104 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id="g117-34"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="587" vert-adv-y="587" xpluscharwidth="19.615000000000002"></glyph.data></g></svg> 400 Hz, 700 Hz, and 2 kHz.</div>

Complexity

CMOS Realization of All-Positive Pinched Hysteresis Loops

Figure 9