Complexity

Volume 2017, Article ID 7863095, 15 pages

https://doi.org/10.1155/2017/7863095

## CMOS Realization of All-Positive Pinched Hysteresis Loops

^{1}Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4^{2}Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, UAE^{3}Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza 12588, Egypt^{4}Physics Department, Electronics Laboratory, University of Patras, Rio, 26504 Patras, Greece

Correspondence should be addressed to B. J. Maundy; ac.yraglacu@ydnuamb

Received 21 March 2017; Accepted 20 June 2017; Published 6 August 2017

Academic Editor: Jesus M. Munoz-Pacheco

Copyright © 2017 B. J. Maundy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.

#### 1. Introduction

Pinched hysteresis was proposed to be a signature of memristive devices [1, 2], yet it can also be observed in several other nonlinear devices such as nonlinear inductors (capacitors) with quadratic-type current (voltage) dependence [3]. Finding a general model for pinched hysteresis behavior was attempted in [4] for specific devices labeled as memristors [5]. In [6] and from a simplified mathematical point of view, the following model was proposed and shown to exhibit a pinched hysteresis behavior which can fit both charge-controlled and flux-controlled memristance definitions:where if and , the charge-controlled memristance is obtained, while for the alternative setting and , the flux-controlled memristance is obtained. In (1), the constants and are scaling and integration time constants, respectively. Note that circuit realization of this model for the purpose of emulating its pinched hysteresis behavior in non-solid-state devices requires a multiplier block, an integrator block, and an adder [6]. Several other emulator circuits have recently been proposed in the literature [7–13]. It is important to note that (1) is nonlinear due to the multiplication term and that pinched hysteresis cannot appear in a linear system. It is also possible to include other forms of nonlinearity that apply to the shaping of the loop as a result of shaping the applied excitation. This means replacing in (1) more generally with .

Pinched hysteresis loop is generally observed as a result of applying a bipolar sinusoidal voltage or current excitation signal and is thus symmetrical around the origin. Nonsymmetrical loops can also be obtained when the pinch point is shifted away from the origin. However, an all-positive pinched loop, to the best of our knowledge, has not been demonstrated before. It is the purpose of this work to introduce two simple circuits where this behavior is observed. We rely on the inherent nonlinearity of a MOS transistor to perform the multiplication operation required by (1) in order to obtain a charge-controlled memristance. Recall that a MOS transistor current-voltage relation can be described bywhere is the drain-to-source current, and are, respectively, the gate-to-source and drain-to-source voltage, is the threshold voltage, and is a constant in units. It is obvious from (2) that a multiplication operation is inherent through the term . However, for an NMOS transistor, the current is unidirectional and the condition is necessary for the transistor to switch on. Therefore, if (2) is successfully reconfigured to implement (1), an all-positive pinched hysteresis loop can be obtained. In the first part of this work, we do not attempt to remove the extra nonlinear term and therefore it remains affecting the pinched loop. However, this effect is minimized via proper selection of the design parameters. In a later section of the work, we employ a linearization circuit to remove this quadratic term and hence ensure that only the multiplication nonlinearity term remains. As a result and comparing (2) to (1) assuming is minimized or eliminated, it is clear that the mapping , , and is necessary. To achieve this, we adopt a frequency-domain approach which also allows independent adjustment of the fixed part and the charge-controlled part of the memristance. We stress and clarify the role played by the capacitors in the proposed circuits, which is crucial to the understanding of pinched hysteresis behavior in general, as clearly seen in [17, 18] for solid-state devices as well. Note that, in reconfiguring (2) to realize (1) via this mapping, we are essentially modifying the MOS transistor transconductance such that it is state-controlled, with the state variable being the terminal voltage of the transconductance . The time constant necessary in (1) can only be obtained with an embedded capacitance (physical or parasitic) [17, 18]. Finally, it must be stated that this paper is concerned with the “pinched hysteresis behavior” as a behavior rather than with proposing yet another memristor emulator. The design concept of the circuits under study here is completely new and relies on a frequency-domain approach rather than a time-domain approach. It also shows for the first time that pinched hysteresis can even be unipolar, something not possible with memristors as they are so defined.

This manuscript is organized as follows. Section 2 looks at the proposed circuits and presents the theory behind their operation that leads to pinched hysteresis behavior. Section 3 computes the memristance of the proposed circuits, with numerical simulations, and presents pinch-off analysis of the proposed circuits. In Section 4, a method to linearize the main transistor in triode is presented which removes the extra nonlinear term in (2). In Section 5, simulation and experimental results are presented, and finally our conclusions are given in Section 6.

#### 2. The Proposed Circuits

Consider the circuits shown in Figure 1 both consisting of opamp connected as a buffer and opamp along with the NMOS transistor as a simple voltage to current converter which converts the voltage of the noninverting terminal of into a current through NMOS transistor . It is essential for to remain in triode, hence acting as a transconductance. Both circuits contain a lossy integrator comprising , and a DC bias voltage required to maintain in triode (, ). The difference between the two circuits can be seen in their high-pass filter sections. In the case of Figure 1(a), it consists of with an additional DC source providing a DC voltage to the drain of . For Figure 1(b), the high-pass filter is made up of and here the drain-to-source DC biasing of comes from through as , where . Note that maintaining transistor in triode in both circuits requires that and for Figures 1(a) and 1(b), respectively.