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International Journal of Antennas and Propagation
Volume 2012, Article ID 851465, 10 pages
Application Article

A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set

1Oriental Institute of Technology, Taipei 22061, Taiwan
2Communication University of China, Beijing 100024, China
3Pennsylvania State University, University Park, PA 16803, USA
42COMU, State College, PA 16803, USA

Received 20 July 2011; Accepted 30 November 2011

Academic Editor: Joshua Le-Wei Li

Copyright © 2012 Dau-Chyrh Chang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant improvement on the simulation performance. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of (vector arithmetic logic unit) VALU acceleration over GPU acceleration. Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set.