Table 3: Critical path delay in ns for different EB's I/O positions as shown in Figure 5 for single EB-type FPGA. The percentage shows the deviation from the 1 side result.

Circuits1 side2 sides3 sides4 sides

(42 wires/clb)(21 wires/clb)(14 wires/clb)(11 wires/clb)

bgm12.01 (0%)11.92 (−0.7%)11.93 (−0.7%)12.03 (0.2%)
dscg12.12 (0%)12.34 (1.8%)12.13 (0.1%)12.28 (1.3%)
bfly12.42 (0%)12.38 (−0.3%)12.30 (−1.0%)12.19 (−1.9%)
ode13.02 (0%)13.30 (2.2%)12.79 (−1.8%)13.06 (0.3%)
mm311.22 (0%)11.53 (2.8%)11.31 (0.8%)11.29 (0.6%)
fir412.63 (0%)12.79 (1.3%)12.41 (−1.7%)12.67 (0.3%)

Average12.23 (0%)12.37 (1.1%)12.14 (−1.9%)12.25 (0.9%)