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International Journal of Reconfigurable Computing
Volume 2010, Article ID 475620, 10 pages
Research Article

Multiloop Parallelisation Using Unrolling and Fission

1Faculty of Information Technology, Macau University of Science and Technology, Taipa, Macau, China
2Department of Computing, Imperial College London, London, UK
3School of Electrical and Information Engineering, University of Sydney, Sydney, NSW, Australia

Received 1 July 2009; Accepted 19 October 2009

Academic Editor: Valentin Obac Roda

Copyright © 2010 Yuet Ming Lam et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop under hardware size constraints. The approach is demonstrated using three applications: speech recognition, image processing, and the N-Body problem. Experimental results show that a maximum speedup of 34 is achieved on a 274 MHz FPGA for the N-Body over a 2.6 GHz microprocessor, which is 4.1 times higher than that of an approach without unrolling.