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International Journal of Reconfigurable Computing
Volume 2010, Article ID 787405, 9 pages
http://dx.doi.org/10.1155/2010/787405
Research Article

Power Characterisation for Fine-Grain Reconfigurable Fabrics

1Department of Computing, Imperial College London, London SW7 2AZ, UK
2Department of EEE, Imperial College London, London SW7 2AZ, UK
3Nokia Devices R&D, Tampere, Finland

Received 1 July 2009; Accepted 22 October 2009

Academic Editor: Elías Todorovich

Copyright © 2010 Tobias Becker et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs) that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.