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International Journal of Reconfigurable Computing
Volume 2011, Article ID 745147, 14 pages
Research Article

An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads

1Department of Electrical and Electronic Engineering, Imperial College London, London SW7 2AZ, UK
2Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA 19104, USA

Received 28 August 2010; Accepted 14 December 2010

Academic Editor: Michael Hübner

Copyright © 2011 Nachiket Kapre and André Dehon. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • Siddhartha, and Nachiket Kapre, “eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. 73–78, . View at Publisher · View at Google Scholar