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International Journal of Reconfigurable Computing
Volume 2011, Article ID 745147, 14 pages
http://dx.doi.org/10.1155/2011/745147
Research Article

An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads

1Department of Electrical and Electronic Engineering, Imperial College London, London SW7 2AZ, UK
2Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA 19104, USA

Received 28 August 2010; Accepted 14 December 2010

Academic Editor: Michael Hübner

Copyright © 2011 Nachiket Kapre and André Dehon. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. R. K. Brayton and C. McMullen, “The decomposition and factorization of boolean expressions,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '82), pp. 49–54, April 1982.
  2. D. Yeung and A. Agarwal, “Experience with fine-grain synchronization in MIMD machines for preconditioned conjugate gradient,” SIGPLAN Notices, vol. 28, no. 7, pp. 187–197, 1993. View at Publisher · View at Google Scholar
  3. M. deLorimier, N. Kapre, N. Mehta et al., “GraphStep: a system architecture for sparse-graph algorithms,” in Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '06), pp. 143–151, April 2006. View at Publisher · View at Google Scholar
  4. N. Kapre and A. DeHon, “Parallelizing sparse matrix solve for SPICE circuit simulation using FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT '09), pp. 190–198, December 2009. View at Publisher · View at Google Scholar
  5. L. G. Valiant, “Bridging model for parallel computation,” Communications of the ACM, vol. 33, no. 8, pp. 103–111, 1990. View at Publisher · View at Google Scholar
  6. T. A. Davis and E. P. Natarajan, “Algorithm 907: KLU, a direct sparse solver for circuit simulation problems,” ACM Transactions on Mathematical Software, vol. 37, no. 3, pp. 1–17, 2010. View at Publisher · View at Google Scholar
  7. G. M. Papadopoulos and D. E. Culler, “Monsoon: an explicit token-store architecture,” in Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 82–91, May 1990.
  8. W. Ho and T. Pinkston, “A methodology for designing efficient on-chip interconnects on well-behaved communication patterns,” in Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p. 377, 2006.
  9. G. V. Varatkar and R. Marculescu, “On-chip traffic modeling and synthesis for MPEG-2 video applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 1, pp. 108–119, 2004. View at Publisher · View at Google Scholar
  10. Y. Liu, S. Chakraborty, and W. T. Ooi, “Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design,” in Proceedings of the 42nd Design Automation Conference (DAC '05), pp. 248–253, June 2005.
  11. V. Soteriou, H. Wang, and L.-S. Peh, “A statistical traffic model for on-chip interconnection networks,” in Proceedings of the 14th International Symposium on Modelling, Analysis and Simulation of Computer and Telecommunication Systems, pp. 104–116, 2006.
  12. J. Balfour and W. J. Dally, “Design tradeoffs for tiled CMP on-chip networks,” in Proceedings of the 20th Annual International Conference on Supercomputing (ICS '06), pp. 187–198, July 2006. View at Publisher · View at Google Scholar
  13. P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, “Performance evaluation and design trade-offs for network-on-chip interconnect architectures,” IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025–1040, 2005. View at Publisher · View at Google Scholar
  14. R. Mullins, A. West, and S. Moore, “Low-latency virtual-channel routers for on-chip networks,” in Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA '04), pp. 188–197, June 2004.
  15. N. Kapre, N. Mehta, M. deLorimier et al., “Packet switched vs. time multiplexed FPGA overlay networks,” in Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '06), pp. 205–214, April 2006. View at Publisher · View at Google Scholar
  16. L. M. Ni and P. K. McKinley, “A survey of wormhole routing techniques in direct networks,” Computer, vol. 26, no. 2, pp. 62–76, 1993. View at Publisher · View at Google Scholar
  17. D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, Norwell, Mass, USA, 1992.
  18. A. Marquardt, V. Betz, and J. Rose, “Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density,” in Proceedings of the 7th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '99), pp. 37–46, February 1999.
  19. D. Greenfield, A. Banerjee, J. G. Lee, and S. Moore, “Implications of rent's rule for NoC design and its fault-tolerance,” in Proceedings of the 1st International Symposium on Networks-on-Chip (NOCS '07), pp. 283–294, May 2007. View at Publisher · View at Google Scholar
  20. A. Caldwell, A. Kahng, and I. Markov, “Improved algorithms for hypergraph bipartitioning,” in Proceedings of the Asia and South Pacific Design Automation Conference, pp. 661–666, January 2000.
  21. J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Enginering Approach, Elsevier, New York, NY, USA, 2003.
  22. C.-W. Tseng, “Compiler optimizations for eliminating barrier synchronization,” SIGPLAN Notices, vol. 30, no. 8, pp. 144–155, 1995. View at Publisher · View at Google Scholar
  23. H. Liu and P. Singh, “ConceptNet—a practical commonsense reasoning tool-kit,” BT Technology Journal, vol. 22, no. 4, pp. 211–226, 2004. View at Publisher · View at Google Scholar · View at Scopus
  24. National Institute of Standards and Technology (NIST), “Matrix market,” June 2004, http://math.nist.gov/MatrixMarket/.
  25. M. deLorimier and A. DeHon, “Floating-point sparse matrix-vector multiply for FPGAs,” in Proceedings of the 13th ACM International Symposium on Field Programmable Gate Arrays (FPGA '05), pp. 75–85, February 2005. View at Scopus
  26. N. Kapre and A. DeHon, “Parallelizing sparse matrix solve for SPICE circuit simulation using FPGAs,” in Proceedings of the 8th International Conference on Field-Programmable Technology (FPT '09), pp. 190–198, December 2009. View at Publisher · View at Google Scholar · View at Scopus
  27. The Programmable Logic Data Book-CD, Xilinx, Inc., San Jose, Calif, USA, 2005.