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International Journal of Reconfigurable Computing
Volume 2012, Article ID 298561, 14 pages
http://dx.doi.org/10.1155/2012/298561
Research Article

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

1Institute for Data Processing and Electronics, Karlsruhe Institute of Technology, 76344 Eggenstein-Leopoldshafen, Germany
2Object Recognition Department, Fraunhofer IOSB, 76275 Ettlingen, Germany
3Institute for Information Processing Technology, Karlsruhe Institute of Technology, 76128 Karlsruhe, Germany
4Chair for Embedded Systems in Information Technology, Ruhr-University of Bochum, 44780 Bochum, Germany

Received 4 May 2012; Accepted 3 October 2012

Academic Editor: René Cumplido

Copyright © 2012 Diana Göhringer et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Diana Göhringer, Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, and Michael Hübner, “Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration,” International Journal of Reconfigurable Computing, vol. 2012, Article ID 298561, 14 pages, 2012. https://doi.org/10.1155/2012/298561.