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International Journal of Reconfigurable Computing
Volume 2013, Article ID 905057, 32 pages
Research Article

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

1Embedded System-on-Chip Group, IKERLAN-IK4 Research Alliance, 20500 Mondragón, Spain
2System Level Integration Group, The University of Edinburgh, Edinburgh EH9 3JL, UK

Received 3 May 2012; Revised 2 October 2012; Accepted 3 October 2012

Academic Editor: René Cumplido

Copyright © 2013 Xabier Iturbe et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined.