International Journal of Reconfigurable Computing / 2017 / Article / Tab 3

Research Article

Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection

Table 3

Device utilization and maximum operating speed of (SOM) defuzzification module.

DesignHardwareTimingUtilization
Design methodDevice familyDevice nameTargeted frequency (MHz)Targeted time (ns)Estimated time (ns)Number of cycles requiredBRAMDSP48EFFLUT

Nonoptimized HLSArtix-7Xc7a100tcsg324-188.333129.791–1200108178
Optimized HLSArtix-7Xc7a100tcsg324-188.3331210.42102055
Optimized HLSArtix-7Xc7a100tcsg324-290.909119.16102055
Optimized HLSArtix-7Xc7a100tcsg324-3100.00108.28102055
Optimized HLSKintex-7Xc7k160tfbg484-1100.00108.21102055
Optimized HLSKintex-7Xc7k160tfbg484-2111.11197.22102055
Optimized HLSKintex-7Xc7k160tfbg484-3125.0086.56102055
RTLArtix-7Xc7a100tcsg324-188.3331211.07100965
RTLArtix-7Xc7a100tcsg324-290.909119.87100965
RTLArtix-7Xc7a100tcsg324-3100.00108.91100965
RTLKintex-7Xc7k160tfbg484-1100.00108.73100965
RTLKintex-7Xc7k160tfbg484-2111.11197.51100965
RTLKintex-7Xc7k160tfbg484-3125.0086.76100965

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