Research Article
Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection
Table 3
Device utilization and maximum operating speed of (SOM) defuzzification module.
| | Design | Hardware | Timing | Utilization | | Design method | Device family | Device name | Targeted frequency (MHz) | Targeted time (ns) | Estimated time (ns) | Number of cycles required | BRAM | DSP48E | FF | LUT |
| | Nonoptimized HLS | Artix-7 | Xc7a100tcsg324-1 | 88.333 | 12 | 9.79 | 1–12 | 0 | 0 | 108 | 178 | | Optimized HLS | Artix-7 | Xc7a100tcsg324-1 | 88.333 | 12 | 10.42 | 1 | 0 | 2 | 0 | 55 | | Optimized HLS | Artix-7 | Xc7a100tcsg324-2 | 90.909 | 11 | 9.16 | 1 | 0 | 2 | 0 | 55 | | Optimized HLS | Artix-7 | Xc7a100tcsg324-3 | 100.00 | 10 | 8.28 | 1 | 0 | 2 | 0 | 55 | | Optimized HLS | Kintex-7 | Xc7k160tfbg484-1 | 100.00 | 10 | 8.21 | 1 | 0 | 2 | 0 | 55 | | Optimized HLS | Kintex-7 | Xc7k160tfbg484-2 | 111.111 | 9 | 7.22 | 1 | 0 | 2 | 0 | 55 | | Optimized HLS | Kintex-7 | Xc7k160tfbg484-3 | 125.00 | 8 | 6.56 | 1 | 0 | 2 | 0 | 55 | | RTL | Artix-7 | Xc7a100tcsg324-1 | 88.333 | 12 | 11.07 | 1 | 0 | 0 | 9 | 65 | | RTL | Artix-7 | Xc7a100tcsg324-2 | 90.909 | 11 | 9.87 | 1 | 0 | 0 | 9 | 65 | | RTL | Artix-7 | Xc7a100tcsg324-3 | 100.00 | 10 | 8.91 | 1 | 0 | 0 | 9 | 65 | | RTL | Kintex-7 | Xc7k160tfbg484-1 | 100.00 | 10 | 8.73 | 1 | 0 | 0 | 9 | 65 | | RTL | Kintex-7 | Xc7k160tfbg484-2 | 111.111 | 9 | 7.51 | 1 | 0 | 0 | 9 | 65 | | RTL | Kintex-7 | Xc7k160tfbg484-3 | 125.00 | 8 | 6.76 | 1 | 0 | 0 | 9 | 65 |
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