International Journal of Reconfigurable Computing

Volume 2017, Article ID 1325493, 13 pages

https://doi.org/10.1155/2017/1325493

## Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection

Electrical and Computer Engineering Department, Western Michigan University, Kalamazoo, MI 49009, USA

Correspondence should be addressed to Aous H. Kurdi; ude.hcimw@idruk.dammahsuoa

Received 5 December 2016; Accepted 8 February 2017; Published 1 March 2017

Academic Editor: Yuko Hara-Azumi

Copyright © 2017 Aous H. Kurdi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

In this paper, the design and the implementation of a pipelined hardware accelerator based on a fuzzy logic approach for an edge detection system are presented. The fuzzy system comprises a preprocessing stage, a fuzzifier with four fuzzy inputs, an inference system with seven rules, and a defuzzification stage delivering a single crisp output, which represents the intensity value of a pixel in the output image. The hardware accelerator consists of seven stages with one clock cycle latency per stage. The defuzzification stage was implemented using three different defuzzification methods. These methods are the mean of maxima, the smallest of maxima, and the largest of maxima. The defuzzification modules are interchangeable while the system runs using partial reconfiguration design methodology. System development was carried out using Vivado High-Level Synthesis, Vivado Design Suite, Vivado Simulator, and a set of Xilinx 7000 FPGA devices. Depending upon the speed grade of the device that is employed, the system can operate at a frequency range from 83 MHz to 125 MHz. Its peak performance is up to 58 high definition frames per second. A comparison of this system’s performance and its software counterpart shows a significant speedup in the magnitude of hundred thousand times.

#### 1. Introduction

Digital system design using Field Programmable Gate Arrays (FPGAs) focuses on performance, device utilization, and rapid development. Xilinx Vivado HLS offers a great development environment that enables the analysis of the system’s performance and design optimization. It also facilitates modularized system design. The Vivado Design Suite provides the means for developing dynamic, partially reconfigurable designs in which different hardware modules can be swapped in and out to utilize available hardware resources on the fly. FPGAs, as a platform, represent one of the most qualified contenders for hardware implementation of digital signal processing systems [1]. In the Xilinx 7 Series devices, the programmable elements organized in blocks called Configurable Logic Block (CLB). Each CLB is comprised of two slices, and each slice is provided with a 6-input 1-output look-up table (LUT), distributed memory, shift register, high-speed logic for arithmetic functionality, a wide multiplexer, and a switching matrix to facilitate the access to routing elements on the chip [2]. The synthesizer tool assigns the chip’s resources, mainly the CLBs, in accordance with the designer choice to implement sequential or combinational logic circuits.

Digital systems by nature rely on Boolean logic. Boolean logic has been, conventionally, the staple of knowledge representation for quite long. The main shortcoming in this regard is the incomplete applicability to situations of uncertainty and inaccuracy [3]. Thus, conventional approaches founded on Boolean logic do not provide suitable frameworks to represent human knowledge that is characterized by the uncertainty and fuzziness associated with the human cognitive function. Fuzzy logic, however, provides a mathematically feasible framework to represent degrees of truth and falsehood in contrast to the classic true or false values of Boolean logic. Fuzzy logic is referred to here in the wide-sense [4] that includes the concept of fuzzy sets [5] and approximate reasoning. For many applications, fuzzy logic has become an indispensable tool. Those applications include system control, intelligent systems, and image processing [6].

Most image processing algorithms contain edge detection as a vital part. Edge detection is, essentially, any method or algorithm that determines the set or sets of points within a digital image at which the gradient of intensity becomes a rapidly increasing or decreasing function of spatial coordinates [7, 8]. These points are grouped into curved line shapes called edges. Different methods have been developed to extract the edges in an image such as the Sobel operator, Laplacian, and Prewitt. These methods use specific parameters, such as a threshold, to complete the edge detection process [9].

Fuzzy logic based edge detection makes use of human knowledge to identify edges. A proposal for an improved edge detection algorithm using fuzzy logic was presented in [10]. The authors therein applied fuzzy logic techniques on a 3 × 3 pixels’ mask. That mask is exploited in the process of examining each pixel’s relation to its neighbor pixels. Each pixel is considered as a fuzzy input resulting in a multi-input-single-output (MISO) fuzzy system. Another approach used the pixels’ gradient and standard deviation values as inputs to the fuzzy system [11]. In this paper, the suggested system works in such a way that it decides on which pixel is considered an edge, or not, by carrying out inference calculations utilizing a set of fuzzy IF-THEN rules. Using fuzzy logic to construct an edge detection algorithm would have the obvious potential. It could incorporate human knowledge and intuition into a model that can adapt to a substantial departure from the expected input images, such as the presence of noise in the input image, rather than using only a single real number to substantiate detection, that is, using a static threshold value. Fuzzy logic based systems work with a linguistic representation of knowledge in a way that describes uncertainty in the form of IF-THEN rules. Complex systems can be modeled using those rules that are intuitively recognizable to human beings [12]. To unlock the potential of fuzzy logic based systems in real life applications, practical platforms with low energy consumption and high computing power are crucially needed to implement them. Authors in [13], worked on utilizing FPGAs in implementing a fuzzy logic controller to track the maximum power point of the photovoltaic system. The authors used the Very High-Speed Hardware Description Language (VHDL) to design and implement a Mamdani-type [13] fuzzy controller.

The partial reconfiguration design approach aims to maximize device utilization efficiency by allowing different functional modules to use a specified set or sets of device resources called reconfigurable partition (PR) in interchangeable fashion while preserving the functionality of the rest of the system. In [14], a proposal for real-time tasks scheduling using partially reconfigurable FPGA design was discussed. The authors suggested dividing the FPGA fabric floor into homogenous blocks. Their experimental outcomes showed high resource utilization efficiency.

The rest of the paper is structured as follows: Section 2 introduces the proposed fuzzy edge detector system. The architecture of the hardware accelerator is described in Section 3. In Section 4, the dynamic partial reconfiguration design component of the edge detector system is discussed. The evaluation of the results is presented in Section 5. Conclusions are given Section 6.

#### 2. The Proposed Fuzzy Edge Detector System

The proposed edge detector is a Mamdani-type [15] fuzzy system with four fuzzy inputs, one crisp output, and a knowledge base made of seven IF-THEN rules. It is important to note that in a Mamdani-type fuzzy system no implication functions [16] are used to create the fuzzy knowledge base representation. The first two inputs are the gradients on the -axis and the -axis out of a kernel of 3 × 3 pixels. and are the associated fuzzy sets, respectively. The third input is the output of a low-pass filter, and the corresponding fuzzy set is named LF, while the final input is the output of a high-pass filter, and the corresponding fuzzy input is referred to by HF.

##### 2.1. Preprocessing

In preprocessing, a kernel of 3 × 3 pixels formed from the input image is used to compute the gradients in -direction and -directions, low-pass filter, and high-pass filter using (1), (2), (3), and (4), respectively. stands for the kernel with the targeted pixel at the center.

##### 2.2. Fuzzification

For fuzzification, crisp inputs are transformed into fuzzy inputs. Linguistic variables were created to represent the fuzzy qualities over a practical range of crisp values. For each linguistic variable three fuzzy sets were defined over the universal sets of discourse, namely, LOW, MED, and HIGH.

##### 2.3. The Inference System

For each input variable, three membership functions (MF) were defined, LOW, MED, and HIGH. LOW and HIGH are trapezoid-shaped MFs while MED is a triangle-shaped one. The membership functions are distributed over the universal set of discourse ranging from 0 to 255 (the intensity range in a grayscale image) as illustrated in Figure 1.