A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations

Table 2

An example of Variant-LUT for Explorer.

Variant no.	No. of slots	()	Performance	Logic slices	BRAM slices	DSP slices
	1	240	8	3093	43	30
	2	120	8	6062	79	54
	1	120	4	3093	43	30
	3	60	8	11877	142	101
	2	60	4	6062	79	54
	1	60	2	3093	43	30
	5	30	8	23259	270	193
	3	30	4	11877	142	101
	2	30	2	6062	79	54
	1	30	1	3093	43	30
	1	240	8	2061	22	82
	2	120	8	4040	36	158
	1	120	4	2061	22	82
	3	60	8	7914	67	304
	2	60	4	4040	36	158
	1	60	2	2061	22	82
	5	30	8	15499	121	589
	3	30	4	7914	67	304
	2	30	2	4040	36	158
	1	30	1	2061	22	82
	1	240	8	5003	27	24
	2	120	8	9806	44	37
	1	120	4	5003	27	24
	3	60	8	19212	79	66
	2	60	4	9806	44	37
	1	60	2	5003	27	24
	5	30	8	37623	142	122
	3	30	4	19212	79	66
	2	30	2	9806	44	37
	1	30	1	5003	27	24
	1	240	8	4009	17	47
	2	120	8	7858	27	86
	1	120	4	4009	17	47
	3	60	8	15395	43	159
	2	60	4	7858	27	86
	1	60	2	4009	17	47
	5	30	8	30148	76	298
	3	30	4	15395	43	159
	2	30	2	7858	27	86
	1	30	1	4009	17	47
	1	240	8	5088	39	51
	2	120	8	9972	68	82
	1	120	4	5088	39	51
	3	60	8	19338	122	148
	2	60	4	9972	68	82
	1	60	2	5088	39	51
	5	30	8	38162	228	274
	3	30	4	19338	122	148
	2	30	2	9972	68	82
	1	30	1	5088	39	51
	1	240	8	2567	33	73
	2	120	8	5011	53	131
	1	120	4	2567	33	73
	3	60	8	9857	92	255
	2	60	4	5011	53	131
	1	60	2	2567	33	73
	5	30	8	19104	164	497
	3	30	4	9857	92	255
	2	30	2	5011	53	131
	1	30	1	2567	33	73