International Journal of Reconfigurable Computing

Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware

FPGA Interconnect Topologies Exploration

Non-Power-of-Two FFTs: Exploring the Flexibility of the Montium TP

Pipeline FFT Architectures Optimized for FPGAs

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings

Software Toolchain for Large-Scale RE-NFA Construction on FPGA

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems

Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms

Analysis and Design of a Context Adaptable SAD/MSE Architecture

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips

A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

An Adaptive Message Passing MPSoC Framework

A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

International Journal of Reconfigurable Computing

Table of Contents

Table of Contents: 2009

Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware

FPGA Interconnect Topologies Exploration

Non-Power-of-Two FFTs: Exploring the Flexibility of the Montium TP

Pipeline FFT Architectures Optimized for FPGAs

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings

Software Toolchain for Large-Scale RE-NFA Construction on FPGA

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems

Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms

Analysis and Design of a Context Adaptable SAD/MSE Architecture

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips

A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

An Adaptive Message Passing MPSoC Framework

A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime