Design Considerations for Autocalibrations of Wide-Band <svg style="vertical-align:-0.0pt;width:27.9px;" id="M1" height="15.025" version="1.1" viewBox="0 0 27.9 15.025" width="27.9" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.022,-0,0,-.022,.062,14.975)"><path id="x394" d="M600 0h-557v24l268 633l28 8l261 -641v-24zM497 50l-194 489l-196 -489h390z" /></g><g transform="matrix(.022,-0,0,-.022,14.431,14.975)"><path id="x3A3" d="M570 168l-39 -168h-498v23l262 301l-248 304v22h471q4 -71 11 -146l-29 -4q-17 65 -37 88q-12 15 -36 20.5t-79 5.5h-181l211 -256l-243 -287h280q51 0 77 20.5t49 83.5z" /></g></svg> Fractional-<svg style="vertical-align:-0.144pt;width:19.7125px;" id="M2" height="14.875" version="1.1" viewBox="0 0 19.7125 14.875" width="19.7125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.022,-0,0,-.022,.062,14.638)"><path id="x1D441" d="M857 650l-6 -28q-44 -4 -61.5 -16.5t-29.5 -48.5q-11 -32 -37 -166l-78 -399h-29l-351 537h-4l-56 -276q-24 -120 -24 -164q0 -35 17.5 -46t75.5 -15l-6 -28h-245l7 28q41 2 62 14t31 44q10 30 41 171l53 245q8 44 6.5 60.5t-14.5 33.5q-10 15 -27 19.5t-64 6.5l6 28h153
l350 -516h5l48 257q25 131 25 171q0 34 -17.5 45t-77.5 15l7 28h240z" /></g></svg> PLL Synthesizers

<table>Loop gain calibration by measuring step-response of PLL (a) Architecture. (b) Operation principle [<a href="/journals/jece/2011/139183/#B10">10</a>, <a href="/journals/jece/2011/139183/#B11">11</a>].</table>

Journal of Electrical and Computer Engineering

fig9

Figure 9

Figure 9: Design Considerations for Autocalibrations of Wide-Band <svg style="vertical-align:-0.0pt;width:27.9px;" id="M1" height="15.025" version="1.1" viewBox="0 0 27.9 15.025" width="27.9" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.022,-0,0,-.022,.062,14.975)"><path id="x394" d="M600 0h-557v24l268 633l28 8l261 -641v-24zM497 50l-194 489l-196 -489h390z" /></g><g transform="matrix(.022,-0,0,-.022,14.431,14.975)"><path id="x3A3" d="M570 168l-39 -168h-498v23l262 301l-248 304v22h471q4 -71 11 -146l-29 -4q-17 65 -37 88q-12 15 -36 20.5t-79 5.5h-181l211 -256l-243 -287h280q51 0 77 20.5t49 83.5z" /></g></svg> Fractional-<svg style="vertical-align:-0.144pt;width:19.7125px;" id="M2" height="14.875" version="1.1" viewBox="0 0 19.7125 14.875" width="19.7125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.022,-0,0,-.022,.062,14.638)"><path id="x1D441" d="M857 650l-6 -28q-44 -4 -61.5 -16.5t-29.5 -48.5q-11 -32 -37 -166l-78 -399h-29l-351 537h-4l-56 -276q-24 -120 -24 -164q0 -35 17.5 -46t75.5 -15l-6 -28h-245l7 28q41 2 62 14t31 44q10 30 41 171l53 245q8 44 6.5 60.5t-14.5 33.5q-10 15 -27 19.5t-64 6.5l6 28h153
l350 -516h5l48 257q25 131 25 171q0 34 -17.5 45t-77.5 15l7 28h240z" /></g></svg> PLL Synthesizers 

Journal of Electrical and Computer Engineering

Design Considerations for Autocalibrations of Wide-Band Fractional- PLL Synthesizers

Figure 9