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Journal of Electrical and Computer Engineering
Volume 2011, Article ID 235843, 9 pages
Research Article

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Institute of Microelectronics, Tsinghua University, Beijing 100084, China

Received 15 May 2011; Revised 5 September 2011; Accepted 9 September 2011

Academic Editor: Sudhakar Pamarti

Copyright © 2011 Ni Xu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.