Table of Contents Author Guidelines Submit a Manuscript
Journal of Electrical and Computer Engineering
Volume 2011 (2011), Article ID 235843, 9 pages
http://dx.doi.org/10.1155/2011/235843
Research Article

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Institute of Microelectronics, Tsinghua University, Beijing 100084, China

Received 15 May 2011; Revised 5 September 2011; Accepted 9 September 2011

Academic Editor: Sudhakar Pamarti

Copyright © 2011 Ni Xu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. R. B. Staszewski, J. L. Wallberg, S. Rezeq et al., “All-digital PLL and transmitter for mobile phones,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2469–2480, 2005. View at Publisher · View at Google Scholar · View at Scopus
  2. J. A. Tierno, A. V. Rylyakov, G. J. English, D. Friedman, and M. Meghelli, “A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 42–51, 2008. View at Google Scholar
  3. C. M. Hsu, M. Z. Straayer, and M. H. Perrott, “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, Article ID 4684627, pp. 2776–2786, 2008. View at Publisher · View at Google Scholar · View at Scopus
  4. M. Lee, M. E. Heidari, and A. A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,” IEEE Journal of Solid-State Circuits, vol. 44, no. 10, article 23, pp. 2808–2816, 2009. View at Publisher · View at Google Scholar · View at Scopus
  5. M. Zanuso, S. Levantino, C. Samori, and A. Lacaita, “A 3 MHz-BW 3.6 GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation,” pp. 476–477. View at Publisher · View at Google Scholar
  6. E. Temporiti, C. Weltin-Wu, D. Baldi, M. Cusmai, and F. Svelto, “A 3.5 GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, Article ID 5604330, pp. 2723–2736, 2010. View at Publisher · View at Google Scholar · View at Scopus
  7. S.-K. Lee, Y.-H. Seo, H.-J. Park, and J.-Y. Sim, “A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, Article ID 5609226, pp. 2874–2881, 2010. View at Publisher · View at Google Scholar · View at Scopus
  8. H.-H. Chang, P.-Y. Wang, J. H. C. Zhan, and B. Y. Hsieh, “A fractional spur-free ADPLL with loop-gain calibration and phase-noise cancellation for GSM/GPRS/EDGE,” in Proceedings of the IEEE International Solid State Circuits Conference, (ISSCC, '08), pp. 200–201, February 2008. View at Publisher · View at Google Scholar
  9. W. Grollitsch, R. Nonis, and N. Da Dalt, “A 1.4 psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '10), pp. 478–479, February 2010. View at Publisher · View at Google Scholar
  10. P.-H. Hsieh, J. Maxey, and C. K. K. Yang, “A phase-selecting digital phase-locked loop with bandwidth tracking in 65-nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, Article ID 5437483, pp. 781–792, 2010. View at Publisher · View at Google Scholar · View at Scopus
  11. D.-S. Kim, H. Song, T. Kim, S. Kim, and D. K. Jeong, “A 0.3–1.4 GHz all-digital fractional-N PLL with adaptive loop gain controller,” IEEE Journal of Solid-State Circuits, vol. 45, no. 11, Article ID 5607237, pp. 2300–2311, 2010. View at Publisher · View at Google Scholar · View at Scopus
  12. T. Tokairin, M. Okada, M. Kitsunezuka, T. Maeda, and M. Fukaishi, “A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, Article ID 5604672, pp. 2582–2590, 2010. View at Publisher · View at Google Scholar · View at Scopus
  13. M. Chen, D. Su, and S. Mehta, “A calibration-free 800 MHz fractional-N digital PLL with embedded TDC,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, Article ID 5610982, pp. 2819–2827, 2010. View at Publisher · View at Google Scholar · View at Scopus
  14. R. He, C. Liu, X. Yu et al., “A low-cost, leakage-insensitive semi-digital PLL with linear phase detection and FIR-embedded digital frequency acquisition,” in Proceedings of the IEEE Asian Solid-State Circuits Conference, (A-SSCC '10), pp. 197–200, 2010. View at Publisher · View at Google Scholar
  15. W. Yin, R. Inti, and P. K. Hanumolu, “A 1.6 mW 1.6ps-rms-Jitter 2.5  GHz digital PLL with 0.7-to-3.5 GHz frequency range in 90 nm CMOS,” in Proceedings of the 32nd Annual Custom Integrated Circuits Conference, (CICC '10), September 2010. View at Publisher · View at Google Scholar
  16. W. Rhee, H. Ainspan, D. J. Friedman, T. Rasmus, S. Garvin, and C. Cranford, “A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5 Gb/s PCI express Gen2 application,” in Proceedings of the IEEE Asian Solid-State Circuits Conference, (A-SSCC '07), pp. 63–66, November 2007. View at Publisher · View at Google Scholar
  17. P.-Y. Wang, J. H. C. Zhan, H. H. Chang, and H. M. S. Chang, “A digital intensive fractional-N PLL and all-digital self-calibration schemes,” IEEE Journal of Solid-State Circuits, vol. 44, no. 8, Article ID 5173739, pp. 2182–2192, 2009. View at Publisher · View at Google Scholar · View at Scopus