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Research Article | Open Access
A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers
This paper proposes a novel wideband LC-based voltage-controlled oscillator (VCO) for multistandard transceivers. The proposed VCO has a core LC-VCO and a tuning-range extension circuit, which consists of switches, a mixer, dividers, and variable gain combiners with a spurious rejection technique. The experimental results exhibit 0.98 to 6.6 GHz continuous frequency tuning with −206 dBc/Hz of FoMT, which is fabricated by using a 0.18 μm CMOS process. The frequency tuning range (FTR) is 149%, and the chip area is 800 μm × 540 μm.
Recently, dozens of wireless communication standards have been used for small mobile terminals, for example, GSM, UMTS, LTE, WiMAX, WLAN, Bluetooth, UWB, GPS, DTV, and RFID, and the standards use several frequency bands spreading in a quite wide range such as 800 MHz to 6 GHz. The mobile terminals have been obtaining multistandard operations, smaller size, and lower power operation . However, the present multistandard RF front end consists of several LNAs, VCOs, mixers, and PAs for each frequency band (Figure 1). A multistandard RF front end implemented in a single chip is required for smaller size, lower power, and more flexible wireless communication terminals such as 800 MHz to 6 GHz. The software defined radio (SDR) has been studied [9, 13], and the multistandard RF front end is also needed to realize the SDR with feasible power consumption. Several multistandard RF front ends have been proposed. Digital-assist architectures are suitable for Si CMOS chips [14, 15]. As a common component for the multistandard RF front ends, this paper proposes a wideband frequency synthesizer covering 0.98 GHz to 6.6 GHz .
2. Previous Work
Ring-oscillator-based VCOs have unacceptably large phase noise for the wireless communication while it has very wide frequency tuning range. Thus, LC-based VCOs are required for the application due to the phase noise requirement. However, the tuning range of LC-based VCOs is usually very narrow such as 2 to 3 GHz even through the 800 MHz-to-6 GHz tuning range is required for the multistandard RF front ends. The conventional LC-VCO cannot overcome the trade-off, so a new wideband LC-based VCO architecture has to be developed.
A VCO using switched capacitors is a well-known topology to extend the tuning range [7, 21], and a switched inductor and a variable active inductor are also utilized [8, 16]. However, these circuits have a trade-off between the phase noise and the tuning range. The VCO using a variable MEMS inductor achieves wide-tuning range with superior phase noise characteristics . However, it is difficult for these pure CMOS VCOs to obtain wide-tuning range with adequate phase noise.
Recently, wideband VCOs for MB-OFDM UWB have been reported [1, 2, 4, 17, 22, 26], which use a tuning range extension technique using QVCO, dividers, and single-sideband mixer (SSBM). These VCOs achieve quite wide tuning range and high spurious rejection using SSBM with signals. However, the VCOs in [1, 2] use two oscillators and have large layout area and larger power consumption. Although the VCOs in [10, 22, 26] use only one QVCO, these VCOs also have larger phase noise and larger power consumption.
Wideband VCOs for multistandard transceivers are also reported [10, 13, 23]. The VCO in  use a QVCO and SSBMs, which also has larger phase noise and larger power consumption. The VCOs in [13, 23] use differential oscillators and 1/2 frequency dividers to avoid utilizing SSBM and the quadrature generation. The VCO in  uses two oscillators, and it requires, moreover, three oscillators for continuous frequency tuning. The VCO in  still requires two oscillators.
The wideband VCO proposed in  uses divide-by-2, divide-by-3, divide-by-4, divide-by-5, divide-by-6, divide-by-8, and divide-by-10 frequency dividers for the tuning range extension. This architecture requires a wideband QVCO, and continuous tuning cannot be realized in the measurement  because tuning range is difficult for QVCOs.
Various topologies for tuning range extension can be utilized depending on the required performances. In this paper, we propose a novel extension architecture to achieve wider tuning range with lower power, smaller layout area, and lower phase noise, which achieves of tuning range from a -range core VCO . The proposed architecture utilizes a differential VCO to generate the fundamental frequency with smaller layout area, lower power consumption, and lower phase noise characteristics than quadrature VCOs. A variable gain combiner is employed to reject spur instead of SSBM.
3. Wideband VCO Architecture
Figure 2 shows the proposed VCO architecture, which consists of a core VCO, two dividers, a switch, a mixer, a high-pass filter, and a combiner . The proposed architecture aims to achieve wider tuning range with lower power and lower phase noise, so a differential VCO and a novel compact frequency extension circuit are introduced. Figure 3 shows frequency plan of the proposed architecture, and , , , and are generated from the fundamental frequency of the core VCO. is generated by the mixer, and is divided from the fundamental frequency . is generated from and , and is also generated as a spurious signal. is divided from . The core VCO is required to have frequency tuning range of , and the total tuning range of can be realized by the frequency extension circuit. For example, tuning range of 2-3 GHz can be extended to 1–6 GHz as shown in Figure 3. Lower frequency can also be generated by a divide-by-2 frequency divider chain .
A differential VCO is employed as the core VCO. Figure 4 shows the schematic of the core VCO, and switched capacitors are utilized for coarse tuning. The differential VCO has better phase noise characteristic than the quadrature VCO, and smaller layout area and lower power consumption can also be achieved. The core VCO has frequency tuning range of more than . At higher frequencies, it is difficult to achieve wide tuning range due to parasitic capacitances, so the lower fundamental frequency is chosen and upconverted to higher frequencies by the mixer.
A CML divider is used as a wideband frequency divider to obtain 1/2 of input frequency, and a wideband mixer shown in Figure 5(a) is used as a frequency multiplier. The mixer is shared to generate and , and input signal of mixer is switched as shown in Figure 2. In case (A) shown in Figure 2, mixer input signals are and , and and are generated. In case (B) shown in Figure 2, both mixer input signals are , and DC and are generated.
(a) wideband mixer
(b) variable gain combiner
In case (A), is the desired frequency and is spurious frequency. The tuning range extension using SSBM requires phases to reject the spurious frequency. In the proposed architecture, output of the first divider has the same frequency as of spur, and it can be used for the spurious rejection instead of the SSBM technique. Therefore, the proposed architecture does not need QVCO and SSBM, and small-size synthesizer can be realized. First, the spurious frequency is rejected by the high-pass filter shown in Figure 2. Second, the remaining spur in the output of filter is rejected by a variable gain combiner shown in Figure 5(b). The gains of combiner are adjusted by bias voltages and . The high-pass filter is also used for phase adjustment, and the filter should be carefully designed to reduce phase mismatch in wide frequency range.
In case (B), is the desired frequency and DC signal is spurious. The DC signal can be suppressed by the high-pass filter. In the proposed architecture, distance to spur is large, which is a desirable feature for spurious rejection in both cases (A) and (B). The proposed architecture is also expected to be robust for LO leak.
Figure 6 shows the detailed block diagram of the proposed wideband VCO. , , , and are output from each node as shown in Figure 6. In the measurement, buffers are utilized for each output. For an actual use, a selector is required, and some switching time is required for the frequency selection.
4. Measurement Result
Figure 7 shows a chip micrograph of the proposed wideband VCO, which is fabricated by using a 0.18 μm CMOS process. Core size is 800 μm × 540 μm. Depicted in Figure 7, the core area is dominated by the spiral inductor for LC-VCO. Signal Source Analyzer (Agilent E5052A) and Spectrum Analyzer (Agilent 8563EC) were used for measurement. GSG probes were also used to obtain on-chip signals. Figure 8 shows the tuning characteristics of the VCO, which exhibits 0.98 GHz to 6.6 GHz oscillation. The right y axis shows the frequency coverage of each output path. The tuning range is found to be 149%. Table 1 summarizes the measured results.
Figure 9 shows spectrum of the combiner output, which contains and of frequency. In this case, is 2.93 GHz. The spurious frequency of is rejected by both the high-pass filter and the variable gain combiner. The total image rejection ratio (IMRR) is 20.2 dB. In this measurement, the bias voltages in the variable gain combiner were manually adjusted.
Figure 10 shows measured phase noise characteristics for as the fundamental frequency and as the final output. The signal is generated through all the circuit blocks shown in Figure 2. This result shows that the proposed wideband VCO operates with the wideband and the low phase noise. Table 2 summarizes the measured phase noise and FoM. The proposed VCO achieves −183 dBc/Hz of FoM for 2.50 GHz oscillation. In this paper, FoMT is also employed to evaluate tuning range in addition to the phase noise. FoMT is defined as the following equation : where is phase noise, is certain frequency offset, is center frequency, and is power consumption. FTR is frequency tuning range, which is defined as . Table 2 also shows FoMT, and the proposed VCO achieves −206 dBc/Hz of FoMT for 2.50 GHz oscillation.
Figure 11 plots performances of wideband LC-VCO reported in the literature [5–8, 10, 11, 16, 18, 21, 24–26], which includes low phase noise VCOs using SOI [24, 25] and BiCMOS processes  and CMOS VCOs using phase noise improvement techniques [5, 11]. The proposed VCO achieves the widest tuning range and the best FoMT simultaneously.
This paper has proposed a novel wideband LC-VCO for multiband applications. The VCO has the core VCO and the tuning range extension circuit. A differential LC-VCO and a double-balanced mixer are utilized instead of a quadrature VCO and a single-sideband mixer for the spurious rejection. In measurement results, the proposed VCO performs 0.98 to 6.6 GHz continuous frequency tuning with −206 dBc/Hz of FoMT, which is fabricated by using a 0.18 μm CMOS process. The frequency tuning range (FTR) is 149%, and the chip area is 800 μm × 540 μm. The proposed VCO achieves the widest tuning range and the best FoMT.
This work was partially supported by JSPS.KAKENHI, STARC, MIC.SCOPE, and VDEC in collaboration with Cadence Design Systems, Inc.
- D. Leenaerts, R. van de Beek, G. van der Weide et al., “A SiGe BiCMOS 1ns fast hopping frequency synthesizer for UWB radio,” in Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '05), pp. 202–593, February 2005.
- J. Lee, “A 3-to-8 GHz fast-hopping frequency synthesizer in 0.18 xμm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 566–573, 2006.
- Y. Kobayashi, K. Ohashi, Y. Ito, H. Ito, K. Okada, and K. Masu, “A 0.49–6.50 GHz wideband LC-VCO with high-IRR in a 180 nm CMOS technology,” in Proceedings of the International Conference on Solid State Devices and Materials, pp. 268–269, September 2007.
- B. Razavi, T. Aytur, C. Lam et al., “Multiband UWB transceivers,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 140–147, September 2005.
- C. Yao and A. Willson, “A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion,” in Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '06), pp. 196–191, February 2006.
- P. Vaananen, M. Metsanvirta, and N. T. Tchamov, “4.3 GHz VCO with 2 GHz tuning range and low phase noise,” IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp. 142–146, 2001.
- A. Fard, T. Johnson, and D. Aberg, “A low power wide band CMOS VCO for multi-standard radios,” in Proceedings of IEEE Radio and Wireless Conference, pp. 79–82, September 2004.
- R. Mukhopadhyay, Y. Park, P. Sen et al., “Reconfigurable RFICs in Si-based technologies for a compact intelligent RF front-end,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 1, pp. 81–91, 2005.
- H. Tsurumi and Y. Suzuki, “Broadband RF stage architecture for software-defined radio in handheld terminal applications,” IEEE Communications Magazine, vol. 37, no. 2, pp. 90–95, 1999.
- D. Guermandi, P. Tortori, E. Franchi, and A. Gnudi, “A 0.83-2.5 GHz continuously tunable quadrature VCO,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2620–2627, 2005.
- A. D. Berny, A. M. Niknejad, and R. G. Meyer, “A 1.8 GHz LC VCO with 1.3 GHz tuning range and digital amplitude calibration,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 909–916, 2005.
- H. Eul, “ICs for mobile multimedia communications,” in Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '06), pp. 31–20, February 2006.
- R. Bagheri, A. Mirzaei, S. Chehrazi et al., “An 800MHz to 5GHz software-defined radio receiver in 90nm CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '06), pp. 469–480, February 2006.
- Y. Yoshihara, H. Sugawara, H. Ito, K. Okada, and K. Masu, “Reconfigurable RF circuit design for multi-band wireless chip,” in Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 418–419, jpn, August 2004.
- K. Okada, Y. Yoshihara, H. Sugawara, and K. Masu, “A dynamic reconfigurable RF circuit architecture,” in Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 683–686, 2005.
- A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS oscillators with switched tuning,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 555–557, May 1998.
- C. Liang, S. Liu, Y. Chen, T. Yang, and G. Ma, “A 14-band frequency synthesizer for MB-OFDM UWB application,” in Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '06), pp. 113–126, February 2006.
- Y. Ito, Y. Yoshihara, H. Sugawara, K. Okada, and K. Masu, “A 1.3–2.8 GHz wide range CMOS LC-VCO using variable inductor,” in Proceedings of the IEEE Asian Solid-State Circuits Conference Digest of Technical Papers, pp. 265–268, November 2005.
- B. Razavi, “Multi-decade carrier generation for cognitive radios,” in Proceedings of the Symposium on VLSI Circuits, pp. 120–121, June 2009.
- Y. Ito, H. Sugawara, K. Okada, and K. Masu, “A 0.98 to 6.6 GHz tunable wideband VCO in a 180 nm CMOS technology for reconfigurable radio transceiver,” in Proceedings of the IEEE Asian Solid-State Circuits Conference Digest of Technical Papers, pp. 359–362, November 2006.
- A. D. Berny, A. M. Niknejad, and R. G. Meyer, “A wideband low-phase-noise CMOS VCO,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 555–558, September 2003.
- A. Ismail and A. Abidi, “A 3.1- To 8.2 GHz zero-IF receiver and direct frequency synthesizer in 0.18 μm SiGe BiCMOS for mode-2 MB-OFDM UWB communication,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2573–2582, 2005.
- P. Nuzzo, K. Vengattaramane, M. Ingels, V. Giannini, M. Steyaert, and J. Craninckx, “A 0.1-5 GHz dual-VCO software-defined ΣΔ frequency synthesizer in 45 nm digital CMOS,” in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium, (RFIC '09), pp. 321–324, June 2009.
- N. Fong, J. Plouchart, N. Zamdmer et al., “A 1V 3.8-5.7 GHz differentially-tuned VCO in SOI CMOS,” in Procedings of the IEEE Radio Frequency Integrated Circuits Symposium, Digest of Papers, pp. 75–78, June 2002.
- J. Kim, J. O. Plouchart, N. Zamdmer et al., “A 44 GHz differentially tuned VCO with 4 GHz tuning range in 0.12 μm SOI CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '05), pp. 416–607, February 2005.
- A. Tanaka, H. Okada, H. Kodama, and H. Ishikawa, “A 1.1V 3.1-to-9.5 GHz MB-OFDM UWB transceiver in 90 nm CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '06), pp. 120–113, February 2006.
Copyright © 2011 Yusaku Ito et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.