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Journal of Electrical and Computer Engineering
Volume 2011, Article ID 871385, 11 pages
Research Article

An Interpolated Flying-Adder-Based Frequency Synthesizer

Department of Computer and Communication Engineering, National Kaoshiung First University of Science and Technology, No. 2, Jhuoyue Road, Nanzih District, Kaohsiung City 811, Taiwan

Received 8 June 2011; Revised 25 August 2011; Accepted 25 August 2011

Academic Editor: Jae-Yoon Sim

Copyright © 2011 Pao-Lung Chen and Chun-Chien Tsai. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle jitter and root-mean-square (RMS) jitter performance. A multiphase all-digital phase-locked loop (ADPLL) provides steady reference signals for the interpolated flying adder. This paper reveals implementation skills of a multiphase ADPLL, as well as an interpolated flying adder. In addition, analytical details of the jitter performance are derived. A test chip for the proposed interpolated FA-based frequency synthesizer was fabricated in a standard 0.18 μm CMOS technology, and the core area was 0.143 mm2. The output frequency had a range of 33 MHz ~ 286 MHz at 1.8 V with peak-to-peak (𝑃𝑘-𝑃𝑘) jitter 215.2 ps at 286 MHz/1.8 V.