A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

Table 1

Performance comparison of the proposed phase detector.

Performance parameter	[3]	[8]	[9]	[10]	This work
CMOS tech	0.13 μm	0.35 μm	0.18 μm	0.13 μm	0.18 μm
Supply	1.2 v	3.3 v	1.8 v	1.2 v	1.8 v
Max freq. (GHz)	2.94	0.1	1	2.1	5 GHz
Dead-zone	NA	NA	Free	NA	Free
Power cons. (mW)	0.496 @ 128 MHz	NA	NA	NA	0.3
Structure	Closed	Open	Closed	Open	Open