A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

Table 4

A performance comparison of proposed circuit with some recent papers.

Performance parameter	[14]	[15]	[16]	[17]	[18]	[7]	This work
CMOS tech (nm)	65	65	65	65	90	180	180
Supply voltage (v)	1	1.2	1.2	1	1.2	1.8	1.8
VCO	Ring	Ring	LC	Ring	Ring	Ring	Ring
Ref. frequency (GHz)	0.645	0.64	104	1.6	0.01	5	3
Locking range (GHz)	0.485–1.011	0.25–1.06	103.05–104.58	NA	3.5–7.1	2.5–7.3	0.5–5
Ref. spur (dBm)	NA	−54.8	−63.8	−47	−64.8	−66.8	−72
Phase noise @ 1 MHz offset (dBc/Hz)	−110.8	−88.6	−80.41	−88	−105	−108.2	−117.6
RMS jitter (ps)	NA	9.6	2.44	4.82	3.8	0.88	0.671
P-t-P jitter (ps)	NA	52.2	18	38	NA	3.21	3.46
Power (mW)	10	1.2	63	0.99	29.64	13.4	11.5
FOM @ 1 MHz offset (dBc/Hz)	−157	NA	−162.57	NA	NA	−190.55	−198.47