Comprehensive Analysis of ZVS Operation Range and Deadband Conditions of a Dual <i>H</i>-Bridge Bidirectional DC-DC Converter with Phase Shift Control

Adam, Ahmed Hamed Ahmed; Chen, Jiawei; Kamel, Salah; Zeinoddini‐Meymand, Hamed

doi:https://doi.org/10.1155/2023/8882417

Journal of Electrical and Computer Engineering

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Research Article | Open Access

Volume 2023 | Article ID 8882417 | https://doi.org/10.1155/2023/8882417

Comprehensive Analysis of ZVS Operation Range and Deadband Conditions of a Dual H-Bridge Bidirectional DC-DC Converter with Phase Shift Control

Ahmed Hamed Ahmed Adam,¹Jiawei Chen,¹Salah Kamel,²and Hamed Zeinoddini‐Meymand³

Academic Editor: Luigi Piegari

Received16 Dec 2022

Revised24 Mar 2023

Accepted24 Apr 2023

Published10 May 2023

Abstract

This study offers a thorough examination of the zero voltage switching (ZVS) operation range and deadband conditions for a bidirectional DC-DC converter with phase shift control, featuring dual H-bridge. The analysis considers the soft switching range of the DAB converter, accounting for the impact of the headband and the ZVS capacitor. By applying the differential equation of the circuit during deadband time, a sufficient constraint for the input and output bridges can be calculated. The findings indicate that as the output voltage increases, the minimum phase shift value required to achieve ZVS decreases, and expanding the phase shift value will expand the ZVS range and reduce switching losses. The study provides simulation results for various operating conditions, validating the theoretical analysis of the proposed system. In addition, the results furnish information about the circuit behavior during the deadband and waveforms. Finally, MATLAB/SIMULINK verifies the simulation results for different operating stages.

1. Introduction

The double-active-bridge (DAB) converters are highly advantageous compared to other bidirectional-isolated topologies due to their small size, low cost, ease of implementation, and ability to achieve zero-voltage-switching (ZVS) [1–5]. As a result, they have been widely adopted in applications requiring bidirectional power transmission. Previous research on isolated bidirectional DC/DC converters has primarily focused on topology, control strategies, and modeling approaches using classical control theory [6–8]. The literature proposes dual-phase-shift (DPS) control [9] to eliminate reactive power, reduce peak current, and power loss in the DAB converter and determine the on/off state of a simple semiconductor. However, this proposal does not examine the ZVS operating range, which is dependent on factors such as voltage conversion ratios and phase change ratios. The loss of ZVS not only reduces efficiency but also causes electromagnetic interference (EMI) issues [10–12].

The authors of [13] introduced a new hybrid switching modulation approach for an isolated bidirectional DC-DC converter used in a DC microgrid energy storage system. This method combines pulse width modulation and hysteresis current control techniques to achieve zero-voltage switching (ZVS) and improved stability under different operating conditions. Nevertheless, this control strategy has some disadvantages, such as circulating current and backflow power in the voltage-fed dual-active-bridge converter during heavy load conditions, as highlighted in [14].

In the study of [15], a phase-shifted modulation (PSM) method was introduced to minimize current ripple in a modular multilevel converter of a bidirectional DC-DC converter, even under unstable operating conditions. This method involves adjusting the phase-shift angle between the pulse width modulation (PWM) signals of the half-bridge cells of the modular multilevel converter. Although effective in reducing current ripple, this PSM method is computationally complex due to its optimization problem formulation. In addition, determining the optimal phase-shift angle requires solving a convex optimization problem, which can be time-consuming [16–18]. Despite the effectiveness of various modulation schemes in achieving ZVS over wide load ranges, it remains challenging to achieve full ZVS capability over the entire load range due to the high implementation complexity [19].

The proposed bidirectional DC-DC converter circuit topology is depicted in Figure 1. The converter can operate in two modes, depending on the power flow direction. The converter comprises two H-bridge structured converters, referred to as bridges one and two, which are isolated by a 5 kHz high-frequency transformer. The first H-bridge has four IGBT-diode switches [S₁₁–S₁₄], with two series-connected IGBTs per leg, and a snubber capacitor connected to each of the IGBTs to achieve zero voltage switching and minimize turn-off overvoltage. The second H-bridge operates at low voltage and is configured with four IGBT-diode switches [S₂₁–S₂₄], connected to a small snubber capacitor to minimize switching loss [20, 21].

(a)

(b)

The converter is bidirectional, and each H-bridge can be primary or secondary depending on the power flow direction. The circuit operates in buck mode when power flows from the high voltage side (HVS) to the low voltage side (LVS) and in boost mode when the power flow is reversed. A deadband is inserted between the interlocked switches in the same bridge to prevent shooting through during commutation, ensuring the reliability of high-voltage and high-power converters [22–31]. However, the deadband may cause waveform distortion and other unexpected transient processes, as depicted in Figure 2. During the deadband, all switches in the same H-bridge module are turned off, including the four switches [S₁₁–S₁₄] on the primary side [24].

This research presents a straightforward theoretical analysis of the steady-state power conditions, the impact of the ZVS capacitor and the deadband on the soft switching operation range of the DAB converter, with varying objectives such as enhancing the ZVS operation range or improving efficiency. The adequate constraints for input and output bridges for soft switching are determined by resolving the differential equation of the circuit during the deadband.

The article is structured as follows. Section 2 provides the operating principle of the proposed DAB bidirectional DC/DC converter. In Section 3, power flow analysis is introduced. Section 4 examines the full-bridge ZVS condition, while Section 5 discusses the converter’s behavior during the dead time. Section 6 provides simulation results for the above method. Finally, Section 7 presents the conclusions drawn from the study.

2. Operating Principle of the Proposed a DAB Bidirectional DC/DC Converter

2.1. The Topology of the Proposed Circuit and Control Strategy

The dual active bridge bidirectional converter uses a single-phase-shift control method to regulate power flow between two DC sources, as shown in Figure 2. The primary H-bridge switches (S₁₁ and S₁₄) and secondary H-bridge switches (S₂₁–S₂₄) have identical gate signals, with complementary signals for S₁₁ and S₁₂ having a 50% duty cycle. This generates a voltage (±) on the primary side of the transformer. Similarly, a voltage (±) is generated on the secondary side by controlling the switches on the secondary bridge with the same signals as the primary bridge, but with an appropriate phase shift to achieve bidirectional power transfer. The primary voltage is represented by , and the phase shift between the two bridges is denoted by DT_hs. The switching frequency is f_s, and T_hs is half the switching period, T_hs = 1/2f_s. The current i_Ls is the sum of the transformer leakage inductance and the auxiliary inductors of the secondary bridge. The equations for a half-cycle are sufficient, given the current waveform’s half-wave symmetry in Figure 2.

L_s is the sum of transformer leakage inductance and auxiliary inductors. ZVS operation was achieved by connecting snubber capacitors parallel to switches. ZVS can be achieved in both leading and full lagging bridges when and change their sign from negative to positive.

2.2. Principle Operation

Based on the on/off state of the switches, there are different operation modes. Figure 3 illustrates the six segments that emerge during each switching cycle. The following assumptions are made in order to simplify the analysis process:(1)The summation of the transformer leakage inductance and the auxiliary inductor current increases from a negative value at the beginning of the switching cycle to a positive value at the end of the half-switching period(2)The converter is operating at a steady state

(a)

(b)

2.2.1. Stage 0 []

S₁₁ and S₁₄ of the first bridge are turned on at this stage. is a positive voltage. The value of is increasing from a negative to a positive value. S₁₁ and S₁₄ were turned off, and the current flow through the body diodes and . Due to this, and switches will operate under ZVS conditions; the secondary current flows through the body diodes D₂ and D₃, while the current will charge the snubber capacitors and . The stage will end when the current reaches zero (see Figure 3(A)). During this mode, the total dynamic current iswhere is the transformer’s secondary voltage generated by the bridge 2, referred primary voltage

2.2.2. Stage 1 []

Switches S₁₁ and S₁₄ are still in the On state, and current flows through them. The current will charge the snubber capacitors of C₁₂ and C₁₃ and discharge the capacitors of C₁₁ and C₁₄. Consequently, the initial voltages of C₁₂ and C₁₃ are VHB, and those of C₁₁, and C₁₄, are zero. On the secondary side, switches S₂₂ and S₂₃ are still on, i_Ls is greater than 0, and current flows through switches S₂₂ and S₂₃ (see Figure 3(B)).

2.2.3. Stage 2 []

At t = t₂, switches S₂₂ and S₂₃ are turned off due to the snubber capacitors C₂₂ and C₂₃, and the dead time stage begins. Secondary currents charge and discharge Snubber capacitors of S₂₂, S₂₃, and S₂₁, S₂₄, respectively. is the voltage across the capacitor, which gets positive from zero.

The voltage of the ZVS capacitor and the inductance current i_Ls in this stage is plotted in Figure 4

(a)

(b)

(c)

Therefore, the voltage of the ZVS capacitor of S₂₂ during the deadtime zone can be expressed as follows:wherewhere is the voltage across C₂₂, z₂ is the resonant impedance, C_ds is the zero-voltage switch capacitor, and is the self-oscillating frequency.

The voltage across C₂₂ and C₂₃ will increase as the voltage across C₂₁ and C₂₄ continues to decrease, allowing S₂₁ and S₂₄ to turn on under ZVS conditions. When charging and discharging have been completed to the point where the voltages of C₂₁ and C₂₄ become zero, while the voltages of C₂₂ and C₂₃ become , current flows through D₂₁ and D₂₄ diodes (see Figure 3(C)). The switches S₂₁ and S₂₄ are turned on after a suitable dead time with zero-voltage switching. Therefore, Table 1 summarized the switches and output capacitance statuses during this stage.

2.2.4. Stage 3 []

At t = t₃, the second bridge’s switch S₂₁ and S₂₄, will be turned on. Due to i_Ls > 0, the secondary current will flow through the body diodes D₂₁ and D₂₄, which will discharge the capacitors C₂₁ and C₂₄. The primary bridges S₁₁ and S₁₄ remain turned on, and current flows through S₁₁ and S₁₄ (see Figure 3(D)). During this mode, the i_Ls are at their maximum.

2.2.5. Stage 4 []

At t = t₃, the deadtime stage is initiated after switches S₁₁ and S₁₄ have been turned off. As a result of the stored energy in the leakage inductance L_s, the current continues to flow through the snubber capacitors. As the snubber capacitors C₁₁ and C₁₄ are being charged, the snubber capacitors C₁₂ and C₁₃ are being discharged. Thus, the voltage across the primary transformer side decreases from positive to zero while the inductance current i_Ls decreases linearly. The equivalent circuit is shown in Figure 3(E). Table 2 summarized the switches and output capacitance statuses during this stage. The leakage inductance L_s resonates with C₁₁, C₁₂, C₁₃, and C₁₄ to charge C₁₁, C₁₄, and discharge C₁₂ and C₁₃. Therefore, we can express the differential equations as follows:where and are the voltages across C₁₁, and C₁₂, respectively, during this stage, and can be obtained.

Taking into account that the initial values of and . From equations (6) and (7), the following equations can be formulated:

Equation (8) can be simplified further towhere

The voltage of the ZVS capacitor and the inductance current i_Ls in this stage is plotted in Figure 5

(a)

(b)

(c)

i_Ls is the inductance current flowing through the snubber capacitors on the primary side and can be expressed as follows:

During this short time, the voltage and will decrease, and the Snubber capacitors C₁₂ and C₁₃ are still being discharged by snubber capacitors C₁₁ and C₁₄, while is negatively increasing from zero. Similarly, when t = t₅ the ZVS capacitors of S₁₁ and S₁₄ are fully charged, and the ZVS capacitors of S₁₂ and S₁₃ are discharged [24].

As a result, the body diodes D₁₂ and D₁₃ become conductive, setting up conditions for S₁₂ and S₁₃ to be turned on with ZVS in the following stage. The ZVS capacitor voltage of S₁₁ can be expressed using equations (6), (7), and (10).where

In Figure 6, several variations of are plotted versus values of the ZVS capacitor at and according to the dead time during this stage. The maximum value of decreases as the capacitor size increases. As a result, has a lower peak value than when and . For the ZVS to operate correctly, the peak capacitor voltage must be obtained during the deadband [6].

2.2.6. Stage 5 []

At the beginning, S₁₂ and S₁₃ are ON, and S₁₁ and S₁₄ are OFF. Transformer leakage inductance and auxiliary inductors flow into the load through D₂₁ and D₂₄, while primary current flows through D₁₂ and D₁₃. At t = t₆, the secondary side current decreases from positive to zero. There is zero voltage turn-on for active switches, and no turn-on loss exists (see Figure 3(F)).

2.2.7. Stage 6 []

At t = t₆, switches S₁₂ and S₁₃ are still on, while switches S₁₁ and S₁₄ are off. Charges on C₁₂ and C₁₃ will discharge through S₁₂ and S₁₃. The primary current will flow through S₁₂, S₁₃, while the negative current of the transformer leakage inductance will flow through S₂₁ and S₂₄. Therefore, S₂₁ and S₂₄ will be turned off at t = t₆ (see Figure 3(G)).

During this period, No switching occurs at t₆. It is a short time interval only to illustrate the conversion of current flow from the mode to the and mode. Therefore, the current will discharge the snubber capacitors of C₁₂ and C₁₃ and charge C₁₁ and C₁₄.

Figure 7 depicts the circuit operation when one leg of bridge one consisting of S₁₁ and S₁₂ operates with zero voltage switching (ZVS). As shown in Figure 2, the current is positive before the deadband time and flows into S₁₁, as seen in Figure 7(a). After S₁₁ turns off, the deadband time starts. As shown in Figure 7(b), C₁₁ charges from zero to VHB, while C₁₂ discharges from VHB to zero. Once C₁₂’s discharge process is complete, the current freewheels through D₁₂. Providing a gating signal at the point when D₁₂ is conducting enables S₁₂ to turn on with ZVS, as shown in Figure 7(d), as the current in D₁₂ decreases to zero and alternates its polarity.

The circuit modes when S₁₁ and S₁₂ operate at ZVS are depicted in Figure 8. During this time interval, prior to the turn-on of S₁₁, the current is negative, as shown in Figure 2, and the switching voltages are illustrated in Figure 8(a). Deadband time initiates once S₁₁ is turned off. As seen in Figure 8(b), the current flowing in commutates to the snubber capacitors, where C₁₁ discharges from VHB to zero, and C₁₂ charges from zero to VHB. Once the charging and discharging are complete, the current freewheels through commutates to the diode D₁₁, where it is negative, as shown in Figure 8(c). As turn-on gate signals are provided to S₁₁, it begins to conduct at zero voltage once the current alternates its polarity, as illustrated in Figure 8(d). Similarly, ZVS can be employed for visualizing other switches.

3. Power Flow Analysis

The power transfer can be controlled by adjusting the phase shift between the transformer’s primary voltage and secondary voltage [32]. In buck mode, power flows from Bridge 1 to Bridge 2 at a voltage conversion ratio of k < 1. The polarity of the and changes from negative to positive as shown in Figure 2. Thus, under steady-state conditions, the average value of the DC current at the bridge 2 i_cd2 must be zero. Based on figure and . The expression of the inductance current can be obtained. Table 3 summarizes the inductor current steady-state expressions for forwarding power flow directions.

Moreover, and . From the above condition, we can express at time , , , and as follows:

Therefore, the average input current can be expressed as

Consequently, the transmission power controlled by SPS can be expressed as a function of the feeding voltage as follows:

The equation (16) indicates that the powers are directly proportional to the phase shift ratio of the two bridges D. By employing a single-phase shift control, one can represent the normalized transmission power in the following manner:where is the maximum power of the converter. Therefore,

Referring to Figure 2, the maximum inductor current () can be expressed as

When the converter operates at full load and the minimum value of the input, while the input current has a maximum value, therefore, under these conditions, the current stress can be determined as follows:

Equation (20) shows that the current stress of the converter is a function of the maximum phase shift, the maximum value of the voltage ratio, and the value of leakage inductance in the SPS control mode.

Figure 9 shows the output power as a function of the phase shift angle. The maximum power is achieved at a phase shift angle of (π/2), as evident from the graph, indicating that equation (16) has reached its maximum and zero transmission power points. In addition, increasing the phase shift ratio results in higher transmission power values. During power transmission in the forward direction, the source-side bridge leads to the load-side bridge, while in reverse mode, the loading side bridge leads to the source side bridge. Figure 9(d) depicts the relationship between current stress and phase shift at different voltage conversion ratios in SPS control under full load. The graph indicates that, with a constant shift ratio D, current stress decreases as the voltage conversion ratio k is reduced. Therefore, it is recommended to decrease the voltage conversion and phase shift ratio as much as possible to minimize the converter’s current stress, reduce losses, and improve efficiency [24, 27].

(a)

(b)

(c)

(d)

4. Full Bridge ZVS Condition

4.1. Zero Voltage Switching Limits

According to the above-given transition analysis, to ensure full ZVS operation, the inductor current should be negative at (t₀) and positive at t₂ and t₄. In order to achieve ZVS in both leading and lagging full bridges, i_Ls (t₂) and i_Ls (t₄) must be greater than zero. However, to realize ZVS at t = t₀, the leakage inductance energy should be greater than the amount of energy required to charge and discharge the output capacitors in the leading bridge. Therefore, the leakage inductance current can be written as follows:

Due to the symmetry of the leakage inductance current , equation (19) describes the maximum inductor current. As , by equation (21), we can write the equation as follows:where is the voltage conversion between the output voltage on the primary side of the converter and the input voltage, equation (22) shows that when k ≥ 1, there is a requirement of D to realize ZVS of the leading bridge. Regarding the lagging leg bridge, to achieve ZVS operation (power transfer from the high voltage side to the low voltage side), the current of the leakage inductance must be positive.

Since , equation (23) can be presented in the following form:

The normalized load resistance R_L can be obtained as

In equation (24), i_cd2 represents output current and D is required to achieve ZVS of the lagging bridge when k ≤ 1. Furthermore, when k ≥ 1, the lagging bridge is usually achieved, which is the limiting condition for ZVS. Whenever k = 1, ZVS is fulfilled for any value of D. The above analysis can be summarized in Table 4.

Figure 10(a) displays the Zero Voltage Switching (ZVS) region of the DAB converters based on equations (22) and (24), where the phase shift is represented on the x-axis, and the relationship between the output and input voltages is shown on the y-axis. The bold curves indicate the operating zone of the DAB converter under ZVS conditions. When k = 1, complete control of ZVS is achievable. However, under light load conditions where k ≠ 1, the ZVS region diminishes. The operational phase shift is determined by the intersection of the k line and the load line R_L. Increasing the phase shift leads to a larger ZVS region and lower switching loss but higher reactive current value and conduction loss, while decreasing the phase shift produces the opposite effect.

(a)

(b)

Figure 10(b) plots the phase shift and ZVS boundaries of the input and output bridges against the voltage gain ratio for different values of the ZVS capacitor. It can be observed that as the ZVS capacitor increases, the ZVS region decreases.

To expand the operating range of ZVS, it is necessary to select the maximum feasible values for L_seq and D_max. The theoretical maximum D value is 0.5, but the output power’s nonlinearity is more severe for a value of D close to 0.5 because the output power’s evolution with D is parabolic [9]. Therefore, the maximum value of the phase shift and leakage inductance is determined by the maximum transmission power as follows:

A phase shift and the power at which ZVS is lost in the converter can be estimated using the following equations:

4.2. Required Dead times

As mentioned in the transition above, the leakage inductance current must be sufficient to complete the charging and discharging of the capacitor. To achieve ZVS, the dead time must be longer than the voltage capacitor connected in parallel across the switch discharging from the DC input voltage to zero V. As a result, the resonance occurs. During stage 4 [t₄, t₅], the voltage across C₁₂ and C₁₃ decreases to zero and is completely discharged at t = t₅, D₁₂ and D₁₃ are conducive naturally. Moreover, the voltage of S₁₂ and S₁₃ is also clamped to zero, and ZVS is achieved when switches S₁₂ and S₁₃ are turned on at this time. In order to ensure that S₁₂ and S₁₃ will turn ON with ZVS, a dead time is necessary between the turn-off of S₁₁ and S₁₄ and the turn-on of S₁₂ and S₁₃. To ensure that D₁₂ and D₁₃ are conducting before turning ON S₁₂ and S₁₃ should be larger than the time of discharging C₁₂ and C₁₃. Accordingly, the dead-time t_dead can be described as follows:

After the leakage inductance current i_Ls discharges C₁₂, C₁₃ completely, the body diodes D₁₂, D₁₃ will be conductive, resulting in an increase in voltage across and equal to the input DC voltage . According to equation (11), the following equation can be derived:

Based on Figure 2, the leakage inductance current must be greater than zero during the whole dead band [t₄, t₅]. This condition can be expressed as follows:

According to (22), condition (30) can be presented in the following form:

Furthermore, the minimum value of the current i_Lsmin is required to achieve zero voltage switching at t = t₅, ensuring that the voltage across S₁₁ and S₁₄ reaches and equal to the input DC voltage . Consequently, the inductance current i_Ls decreases linearly, as shown in Figure 2. Hence, at , the ; and , and . Therefore, at , and ; and , and . The magnitude of should be greater than i_Lsmin so that the inductance current will fully charge the snubber capacitors C₁₁ and C₁₄ while the voltage across S₁₁ and S₁₄ reaches the input DC voltage . Therefore, we say:

represents the amount of energy transferred, assuming no loss occurs at the circuit. ZVS operates under the condition that during this stage, therefore

The following expression can be obtained by comparing (32) and (33):

The magnitude of should be greater than i_Lsmin in order to ensure that the inductance current fully charges the snubber capacitors C₁₁ and C₁₄ while the voltage across S₁₁ and S₁₄ reaches the input DC voltage . Due to this,

If equation (29) is not satisfied, the amount is smaller than i_dc1min. As a result, the C₁₁ and C₁₄ are not charged up to , while the C₁₂ and C₁₃ are not discharged to zero. Therefore, the zero voltage switching operation cannot be achieved. The efficiency will decrease as a result of switching loss. Accordingly, the voltage of S₁₂ can be expressed as follows:

Thus,where t is the time after the dead time started. At the end of the dead time t = t₅, is not zero because . C₁₂ is shorted out and discharges rapidly from to zero. C₁₁ suddenly charges from to . During dead time, the S₁₁ voltage must reach to ensure S₁₂ will turn on with ZVS. Accordingly,

Formulas (10) and (13), as well as (36) and (38), can be used to determine sufficient restrictions for input bridge ZVS operation:

Formula (39) guarantees that the amount of L_s is sufficient to fully charge the zero-voltage switching capacitor of switch S₁₁. Conversely, during the deadband, formula (40) ensures that across S₁₁ reaches the input DC voltage . As a result, the minimum value of the deadband zone or the maximum value of the ZVS capacitor can be limited [31].

A sufficient constraints output bridge requires the voltage across S₂₂ to reach the output DC voltage during the headband. Consequently,

5. Behaviour of Converter during the Deadtime

Figure 11 illustrates a simulation of the switching waveforms during the operational states. When the time reaches t = t₀, the HV bridge enters its deadtime phase, causing the AC inductor current to flow from the active switches to the opposite antiparallel diode pair. This leads to the primary H-bridge being ahead of the secondary H-bridge, resulting in no phase shift error being detected [33, 34].

As a consequence, when the dead time commences at t = t₁, the output voltage of the LV bridge remains unchanged in polarity. The AC inductor current flowing in the anti-parallel diode of the LV bridge prevents the switching transition from altering the transmission path.

Since the phase shift error (D_db) is caused by the current that slews during the deadtime period, an expression that describes the slew time (D_s) can be derived [33]. Also, since the AC inductor current is cyclic and half-wave symmetric, the positive peak current and the negative peak current have the same magnitude . This means that by setting , a method for deriving this expression is presented in [34], an expression for D_s can be solved for both the leading and lagging switching alternatives aswhere D_c represents the commanded phase shift, and D_DT is the deadtime period in radians. From the slew time equation (42), the phase shift error D_db is determined by first identifying the converter operating condition. This is necessary because the phase shift error augments the applied phase shift when the HV bridge leads the LV bridge and reduces it when the HV bridge lags the LV bridge. This allows D_db to be determined based on D_s. The relationship between D_s and D_db is therefore summarized in Table 5.

6. Simulation Results

MATLAB Simulink was used to simulate the circuit schematic shown in Figure 1 in order to verify the previous theoretical considerations. Table 6 contains the specifications and parameters of the system.

The simulation outcomes for the gating signals and steady-state operation waveforms in the buck mode at 5 kW rated power and a high-frequency transformer are demonstrated in Figure 12, which is consistent with the waveform simulated in Figure 2. The primary voltage of the transformer, the output voltage of the secondary bridge, the voltage across an inductor, and the inductor current all exhibit the same attributes as the fundamental operating waveform of the bidirectional forward converter depicted in Figure 2.

Figure 13(a) shows waveforms of the gate signals and applied to S₁₁ and S₁₂, and are the voltages across S₁₁ and S₁₂, respectively, and i_Ls. It can be seen that the currents i_Ls > 0 and i_Ls < 0 during the turn-on instants of S₁₂ and S₁₁, respectively. The zoomed views of S₁₂ and S₁₁ when turned On are shown in Figures 13(b) and 13(c), respectively. The S₁₁ starts to turn OFF at t = τ_α. For t ≤ τ_α, and are zero and 270 V, respectively (see Figure 13(c)). It can be observed that after t = τ_α, decreases until it equals zero, while increases linearly to 270 V. When t = τ_α1, the S₁₂ will turn on. In addition, before t = τ_α1, = 0, and i_Ls is positive at t = τ_α1. Therefore, D₁₂ conducts from t = τ_α1 to t = τ_α2. The switch S₁₂ conducts from t > τ_α2 as i_Ls become negative. It can be seen from Figure 13(c) that = 0 at t = τ_α1, indicating the ZVS turn-on conduction of S₁₂. Similarly, as can be seen from Figure 13(b), i_Ls become positive concerning t > τ_β1, so after t = τ_β2, S₁₁ begins to conduct at zero voltage = 0. Similarly, you can predict the ZVS operation of the bridge-2 converter.

(a)

(b)

(c)

Figure 14 depicts a comparison between the simulation results of this study and a previous one [8], in terms of the minimum phase shift needed for the input and output bridges to meet the necessary and sufficient constraints for various output voltages. The graph demonstrates that for the lagging bridge, the minimum phase shift required to achieve ZVS decreases as the output voltage increases. On the other hand, for the leading bridge, as the output voltage increases, the minimum phase shift required to achieve ZVS increases. As a result, increasing the phase shift can widen the ZVS range and reduce switching losses, but it can also increase reactive current and conduction losses. Conversely, reducing the phase shift can lead to the opposite results. Therefore, to achieve a successful design, it is crucial to evaluate the trade-off between these factors.

(a)

(b)

The boundaries for zero voltage switching (ZVS) are presented in Figure 15, where the power handled by the converter is depicted on the x-axis. By selecting a value of K that is marginally above 1, the operating range of the converter with ZVS can be substantially expanded.

(a)

(b)

Table 7 shows the comparison simulation results of the value of the phase shift and the power at which ZVS is lost in the leading and lagging bridge between this paper and compared reference paper [8] for different values of the output voltage. Using the value of k equal to 1, the ZVS operation will be lost approximately at 0, 400 and 750 W when the sufficient boundaries to operate with D_ZVS are 0, 0.0167, and 0.02, respectively, for the leading bridge (input bridge). While the ZVS operation will be lost approximately for the lagging bridge at 3200, 2150, and 1250 W, when the sufficient boundaries to operate with D_ZVS are 0.054, 0.049, and 0.025, respectively, for the reference paper [8] (see Figures 14(a) and 15(a) and Table 6). Furthermore, as can also be seen from the Figures 14(b) and 15(b) and Table 6, ZVS operation will be lost approximately at 100, 400, and 1000 W when D_ZVS are 0.0125, 0.016, and 0.04 for the leading bridge. While the ZVS operation will be lost approximately for the lagging bridge at 1700, 740, and 250 W, when the sufficient boundaries to operate with D_ZVS are 0.0125, 0.016, and 0.04, respectively. Moreover, the operating range using ZVS can greatly increase when the k value is slightly larger than one.

When the phase shift of a dual active H-bridge bidirectional DC-DC converter is increased, the duration of overlap between upper and lower switches is reduced, leading to a decrease in switching losses. However, increasing the phase shift also causes an increase in conduction losses and reactive current, as the switching devices are subjected to higher voltage stress, resulting in increased conduction losses. In addition, the increase in reactive current results in losses from the converter’s reactive components. This can cause a decrease in the efficiency of the converter. Figure 16 illustrates power efficiency curves that vary with load variation, and the efficiency is significantly low under light load conditions due to ZVS being under the RMS phase current. The RMS currents through the switches determine conduction losses. Under heavy load conditions, the converter is highly efficient because the circulating current decreases, resulting in low conduction losses.

7. Conclusions

This article presents a detailed theoretical analysis of the steady-state power conditions, the impact of the ZVS capacitor, and the deadband on the soft switching operation range of the DAB converter with phase shift control. The simulation results are in agreement with the theoretical analysis. The adequate conditions for achieving ZVS are calculated for both the input and output bridges, and the boundaries of sufficient conditions for ZVS operation are plotted. A comparison of sufficient constraints between our proposed system and previous studies is provided, indicating that our proposed restrictions are more accurate. The study shows that as the output voltage increases, the minimum phase shift value required to achieve ZVS decreases. Increasing the value of D expands the ZVS range and reduces switching losses, as noted in [9].

Abbreviations

ZVS:	Zero voltage switching
DC:	Direct current
DAB:	Dual active bridge
DPS:	Dual phase shift
IGBT:	Insulated gate bipolar transistor
HVS:	High voltage side
LVS:	Low voltage side
SPS:	Single phase shift
D:	Phase shift
D_s:	Slew time
D_db:	Phase shift error
D_c:	Commanded phase shift
D_DT:	Deadtime period in radians.

Data Availability

The data used to support the study are included in the paper.

Conflicts of Interest

The authors declare that there are no conflicts of interest.

Acknowledgments

A portion of this paper was published at the 2019 IEEE International Conference on Environment and Electrical Engineering and 2019 IEEE Industrial and Commercial Power Systems Europe under the title of ZVS Operation Range Analysis and Deadband Conditions of A dual H-bridge Bidirectional DC-DC Converter with Phase Shift Control. This work was supported in part by the Graduate Research and Innovation Foundation of Chongqing under Grant nos. CYS18051 and CYB18062 and in part by the National Natural Science Foundation of China under Grant no. 51877019.

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Copyright © 2023 Ahmed Hamed Ahmed Adam et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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