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Journal of Nanotechnology
Volume 2011 (2011), Article ID 823680, 4 pages
http://dx.doi.org/10.1155/2011/823680
Research Article

All-Printed Thin-Film Transistor Based on Purified Single-Walled Carbon Nanotubes with Linear Response

1Department of Electrical and Computer Engineering, University of Massachusetts Lowell, One University Avenue, Lowell, MA 01854, USA
2Advanced Technologies R&D, Brewer Science, Inc., 2401 Brewer Drive, Rolla, MO 65401, USA
311821 Sterling Panorama Ter, Austin, TX 78738, USA
4Omega Optics, 10306 Sausalito Drive, Austin, TX 78759, USA
5Microelectronics Center, University of Texas Austin, 10100 Burnet Road, Austin, TX 78758, USA
6Electrical Engineering, Ingram School of Engineering, Texas State University, San Marcos, TX 78666, USA
7Optomec, Inc., 3911 Singer Boulevard NE, Albuquerque, NM 87109, USA

Received 29 April 2011; Revised 1 July 2011; Accepted 7 July 2011

Academic Editor: Yoke Khin Yap

Copyright © 2011 Guiru Gu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We report an all-printed thin-film transistor (TFT) on a polyimide substrate with linear transconductance response. The TFT is based on our purified single-walled carbon nanotube (SWCNT) solution that is primarily consists of semiconducting carbon nanotubes (CNTs) with low metal impurities. The all-printed TFT exhibits a high ON/OFF ratio of around 103 and bias-independent transconductance over a certain gate bias range. Such bias-independent transconductance property is different from that of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the special band structure and the one-dimensional (1D) quantum confined density of state (DOS) of CNTs. The bias-independent transconductance promises modulation linearity for analog electronics.

1. Introduction

Printable flexible electronics technology offers a cost-effective way to achieve mass production of large-area flexible electronic circuits without using special lithography equipment. It is expected to offer an enabling technology for numerous applications, particularly those that require or may benefit from the use of flexible polymeric substrates, such as inflatable antennas, electronic papers, RF identification (RFID) tags, smart skins, and flat panel displays. Due to its mechanical flexibility and high field effect mobility, carbon nanotube (CNT) has shown great promises in printable flexible electronics [15]. High mobility and high-speed CNT-based printable thin-film transistor (TFT) have been demonstrated [610]. In addition to its mechanical flexibility and high field effect mobility, CNT is also a promising material for transistors with bias-independent transconductance due to the special band structure and the one-dimensional (1D) quantum confined density of state (DOS) of CNTs [1114]. The band structure and the 1D DOS of CNT allow the CNT-based TFTs to possess near-ballistic electron transportation and bias-independent transconductance [12, 13]. Such bias-independent transconductance is called inherent linearity [12] (referred it to as linear response or linear CNT-TFT, henceforth). The bias-independent transconductance is different from conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and is highly desired in many analog RF devices such as low noise amplifiers and power amplifiers [1113]. However, most linear CNT-TFTs reported to date are based on CNTs grown by using the chemical vapor deposition (CVD) grown method [12, 13] to obtain semiconducting CNTs with good alignment between the source (S) and drain (D) electrodes [13]. While high density aligned CNTs can achieve the highest performance [13], however, due to the high CVD-growth temperature of over 900°C, the CVD grown CNTs are not suitable for the development of printed flexible electronic devices [9]. Purified CNT solutions allow one to print CNT networks on flexible substrates with high field-effect electron mobility [9] and high-speed performance [10] for above-mentioned low-cost printed flexible electronics applications. In this paper, we evaluate the linear response of a CNT-TFT printed at room temperature using our purified single-walled carbon nanotube (SWCNT) solution consisting primarily of semiconducting carbon nanotubes (CNTs) with low metal impurities. The all-printed TFT shows a high ON/OFF ratio of around 103 and bias-independent transconductance over a certain gate bias range. Subthreshold swings of the all-printed TFT are also analyzed and agree well with the CVD-grown CNT-TFTs [12, 13]. The linear response shows that the printed CNT-TFT is promising for analog electronics that requires modulation linearity.

2. Experiment

The all-printed SWCNT-TFT is in a top-gated configuration. It consists of source (S) and drain (D) electrodes, a carrier transport layer based on the purified SWCNT thin film, a gate dielectric layer, and a top gate electrode (G). The highly pure, additive-free, aqueous, SWCNT ink is prepared by Brewer Science Inc. The average tube diameter of the SWCNT is 0.8 nm. The length of the SWCNT varies from a few hundred nm to 1 μm. The trace metal impurity concentration is measured to be <500 ppb. The width (W) of the source and drain electrodes is 500 μm, and the separation between the source and drain electrodes, that is, channel length (L), is 50 μm. All of these TFT elements were printed on a DuPont Kapton FPC polyimide film [15] by using an Optomec’s Aerosol Jet printing system [16]. The source and drain electrodes were first printed on the Kapton FPC polyimide film using UTD Ag silver nanoink from UT-Dots. The active carrier transport layer was then printed, followed by the printing of the gate. Detailed printing process of the SWCNT-TFT is reported elsewhere [10].

3. Results and Discussion

Figure 1 shows the source-drain I-V characteristics ( versus ) of the SWCNT-TFT at different gate voltages () from −2.0 V to +2.0 V. At the same source-drain voltage (), the drain current () decreases as the gate voltage increases from −2.0 V to 2.0 V, suggesting that the SWCNT layer is a p-type carrier (hole) transportation channel [10]. At low source-drain voltages , the gate voltage of +2.0 V can effectively reduce the drain current.

823680.fig.001
Figure 1: Source-drain I-V characteristics ( versus ) of the CNT-TFT at different gate voltages (). At the same source-drain voltage (), the drain current () decreases as the gate voltage increases from −2.0 V to 2.0 V, suggesting that the SWCNT layer is a p-type carrier (hole) transportation channel.

At a gate bias of 0 V, a turn-on voltage of 1.0 V is observed, indicating Schottky barriers formed between the CNT and the source (S) and drain (D) electrodes. At the gate biases of 1.0 V and 2.0 V, a larger turn-on voltages of 1.3 V and 1.4 V are measured, respectively. This reflects that the SWCNT band-bending can be tuned by the gate bias, which changes the Schottky barriers and leads to the turn-on voltage variations. At a gate bias of −1.0 V, a nearly linear I-V curve is obtained, indicating the transition from Schottky barrier to Ohmic contact at the SWCNT and the and electrode interfaces.

Figure 2 shows the drain current, the , versus curve at the source-drain voltages of −0.3 V. As the gate voltage increases from −2.0 V to +2.0 V, the drain current voltages decreases from (A) to (A). If one defines ON and OFF states to be the maximum and minimum steady drain currents , respectively, a high ON/OFF ratio of ~103 is obtained with a low gate voltage tuning from −2.0 V to +2.0 V. Since metallic CNTs are conducting materials that are not affected by the gate field effect, the low drain current at the OFF state and the effective gate control of the SWCNT channel indicate that the concentration of the metallic CNT is low in the SWCNT-TFT and the SWCNT is primarily semiconducting CNT.

823680.fig.002
Figure 2: Drain current versus curves at the source-drain voltage of −0.3 V. A high ON/OFF ratio of ~103 is obtained.

Figure 3 shows the drain current versus curves at different source-drain voltages . The inset in Figure 3 shows the testing configuration. The versus curves can be divided into three regions separated by dashed lines. The three regions are marked in Figure 3 as I, II, and III, respectively. The regions have different transconductances . Region I is when  V, the drain current varies little with the gate bias voltage (referred to as the saturation region henceforth). The transconductances in this region are low (~−2 μA/V) for all the different source-drain voltages from 0.5 V to 2.0 V. Region II is between the two dashed lines. In this region, the versus curves are linear (referred to the linear region henceforth). The transconductances at different in the region are listed in Table 1.

tab1
Table 1: Transconductance at different in the linear region.
823680.fig.003
Figure 3: Drain current versus curves at different source-drain voltages . The inset shows the testing configuration. The versus curves can be divided into I, II, and III regions separated dashed lines.

In Table 1, it is shown that the transconductance varies little with and it stays as a constant when > 1.0 V. For a conventional MOSFET, the drain current is related to the in the linear region by the following equation [17]: where is the mobility of an electron, is the oxide capacitance per area, is the channel length, and is the threshold voltage. From (1), the transconductance of a conventional MOSFET is proportional to , whereas it is independent of for the all-printed SWCNT-FET in Region II. The difference is attributed to the 1D quantum confined DOS of CNTs [12].

Region III is located to the right side of the second dashed line where the gate biases are positive. Figure 4 shows the logarithmic plots of the versus curves in this region. Linear dependence of natural logarithm of the drain current on the gate voltage is obtained in this region, indicating exponential dependence of the drain current on the gate voltage . This is similar to a conventional MOSFET in the subthreshold region [17]. The subthreshold slopes are calculated to be 2.1 V/decade, 5.2 V/decade, and 10.3 V/decade at the drain voltages of 1.0 V, 1.5 V, and 2.0 V, respectively. The subthreshold I-V characteristics of an ideal CNT TFT can be expressed as [12] where is the charge of an electron, is the Planck's constant, is the Boltzmann's constant, and is the threshold voltage. Equation (2) shows that below threshold the drain current has an exponential dependence on at a rate of  mV at room temperature . However, the printed SWCNT TFT shows a lower exponential dependence rate of 0.9 V, 2.2 V, and 4.5 V, at the drain voltages of 1.0 V, 1.5 V, and 2.0 V, respectively. The lower subthreshold slope was also reported [18]. This indicates that the gate bias has a less effective control of the drain current ID than the ideal CNT TFT. This is possibly due to the electric field screening of the gate bias due to the movement of local charges (electron or ions) stored in the gate dielectric [19]. This electric field screening effect is subject to further investigation.

823680.fig.004
Figure 4: Logarithmic plots of the versus curves in the region III of Figure 3. The dashed lines indicated linear dependence of natural logarithm of the drain current on the gate voltage .

4. Conclusion

In this paper, we demonstrated an all-printed flexible TFT based on the purified SWCNT solution. A high ON/OFF ratio of ~103 is obtained. The SWCNT-TFT also shows a linear transconductance region where the transconductance varies little with source and drain voltage bias . Subthreshold swings of the all printed TFT are also analyzed and agree well with the CVD-grown CNT-TFTs [12, 13]. The preliminary demonstration of the linear TFT with high ON/OFF ratio bias-independent transconductance indicates that all-printed flexible TFT based on the purified SWCNT solution is promising for analog RF electronics applications.

Acknowledgments

This research is supported by AFOSR, under Award FA9550-08-1-0070, and NSF STTR Phase II, under Award IIP0924536, and NASA SBIR Phase II, under contract no. NNX09CA37C.

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