Quantization Effects on Period Doubling Route to Chaos in a ZAD-Controlled Buck Converter
Figure 3
Bifurcation diagrams varying and the ADC resolution. ((a)–(c)) Voltage error diagrams () for 8, 12 and 16 bits, respectively. ((d)–(f)) Current error diagrams () for 8, 12, and 16 bits, respectively. ((g)–(i)) Duty cycle diagrams for 8, 12, and 16 bits, respectively.
