An Accurate Hardware Sum-of-Cisoids Fading Channel Simulator for Isotropic and Non-Isotropic Mobile Radio Environments

Table 1

Hardware resource analysis of the SOC fading channel simulator for an implementation in a virtex5 XC5VLX110T-3FF1136 using 𝑁=32 cisoids.

Used elements	Datapath bit-width
	16	18	24	32
Number of slice registers	609	675	873	1086
Number of slice LUT	708	768	975	978
Number of RAMs (𝑁×WL)	4	4	4	4
Number of ROMs (32×WL bits)	3×2	3×2	3×2	3×2
Number of multipliers	6	6	6	6
Number of adders	16	16	16	16