Research Article  Open Access
A Test Data Compression Scheme Based on Irrational Numbers Stored Coding
Abstract
Test question has already become an important factor to restrict the development of integrated circuit industry. A new test data compression scheme, namely irrational numbers stored (INS), is presented. To achieve the goal of compress test data efficiently, test data is converted into floatingpoint numbers, stored in the form of irrational numbers. The algorithm of converting floatingpoint number to irrational number precisely is given. Experimental results for some ISCAS 89 benchmarks show that the compression effect of proposed scheme is better than the coding methods such as FDR, AARLC, INDC, FAVLC, and VRL.
1. Introduction
According to Moore’s law, the integration level of the microchips doubles every 18 to 24 months. As a result, the volume of test data increased dramatically; the test costs become higher; the contradictions between test efficiency and test quality are sharpening. The test data compression technology comes into being to solve the above problems.
Coding compression technology has been widely used because it has such advantages as simple encoding and decompression structure which is independent of the tested chip. A certain encoding scheme is used to encode the original test set. The length of the encoded data is less than the original test set, so as to reduce the test data.
The test set is divided into the sequences of specific law, which can be replaced with new codeword generated by some kinds of coding method. According to the change rule of the length from the original sequence to the codeword, coding methods can be divided into four categories. The first category is fixedtofixed coding method, such as dictionary code [1]. The second category is fixedtovariable coding method, such as Huffman code [2], 9C code [3]. The third category is variabletofixed encoding method, such as runlength code [4]. The fourth category is variabletovariable coding method, such as Golomb code [5], FDR code [6], EFDR code [7], and alternation and runlength code [8].
Among them, the compression method of the first category is the most simple one, but it has the lowest compression efficiency. The compression efficiency of the fourth category is high, but its hardware overhead is larger. The second and third categories have good applicability, which are between the first and fourth categories in terms of compression method, compression efficiency, hardware overhead, and so forth.
It is a new original method to use irrational number to compress test data. It is creative. A scheme of test data compression based on irrational number dictionary code [9] is presented. The encoding rule of this scheme is simple, and the do notcare bit need not be assigned, but it takes extra storage space to store the data dictionary additionally.
A new test data compression scheme based on irrational numbers stored (INS) is presented. It is a fixedtovariable coding method, which has simple encoding rule and can obtain good compression effect. In this scheme, the test set is converted into floatingpoint numbers firstly, and then the floatingpoint numbers are converted into irrational numbers in form of (where the numbers and are integers) by the successive approximation method. So the storage of the test set can be translated into the storage of radicand (integer) and root number (integer). The minimum of corresponding radicand and root number can be found with faster convergence speed. Better compression effect can be obtained when using the INS coding scheme.
The organization of the paper is as follows. Section 2 explains the algorithm of the proposed scheme and gives an example. Section 3 proves the feasibility of the algorithm of the proposed scheme theoretically. The structure of decompressor is presented in Section 4. Section 5 reports the experimental results and analyzes the compression ratio theoretically. Finally Section 6 concludes the paper.
2. INS Coding
In this section, the algorithm of INS coding is described firstly. Then, the flowchart of the scheme is given. Lastly, an example is provided.
2.1. Encoding Rule
The concrete steps of INS coding are as follows.(1)At first, generate the determinate complete test set named by automatic test pattern generation tools.(2)Then cascade the entire test vector, and connect the head of a vector to the tail of previous vector, remembered as .(3)Take the first bits of the test set, and then convert them into a hexadecimal number every four bits a group according to the rules shown in Table 1. Add a decimal point after the first digit, and a hexadecimal floatingpoint number named is formed.(4)Calculate the value of and in the formula , by dichotomy to successive approximate . In this scheme, if the first several bits of and the root of are exactly the same, that is to say, the two are approximately equal to, then consider the following. (I) Calculate first; set , , . (II) Calculate , if its value is equal to , note , , and then go to step (5). Otherwise, calculate , if its value is equal to , note , , and then go to step (5). (III) Consider, and . (IV) Set , calculate , if its value is equal to , note , and then go to step (5). If its value is greater than , . If its value is less than , . Repeat step (IV) until , and then go to step (V). (V) If top is less than , set , . Otherwise, set , . Repeat step (4) until is valid and go to step (5). In this step, the median is always integer in operation process. That can reduce the computation complexity, save the running time, and accelerate the operation process.(5)Encode and in the form of CEBM [10]. Remove the first bits of and repeat steps (3) and (4), until is empty.

Figure 1 shows the detailed flowchart of the scheme.
CEBM is shown in Table 2. Because , , the runlength starts from 2. The first column is the length of runs and the second column is the number of group. The third column is odd bits of the codeword and the fourth column is even bits. The last column is the corresponding codeword. As can be seen, CEBM has the following characteristics. (1) The length of the odd bits and the even bits is equal to every codeword. (2) The odd bits show the runlength. Add data “1” before the odd bits; the new odd bits are just the corresponding binary number of the runlength. The even bits show the end of the codeword. The codeword continues if the even bit is 0 and finishes if it is 1. (3) The length of codeword increases by two bits from group to group ; both the odd bits and the even bits increase one bit. (4) Group contains elements. (5) The corresponding relationship between the runlength and group is like .

For an example, the codeword of 9 is 000011. The odd bits are 001 and the even bits are 001. The even bit needs to be monitored when decoding. If the even bit is 0, it means that codeword continues. If the even bit is 1, it means that codeword finishes. Add data “1” before the odd bits (001); we can get the data 1001, whose corresponding decimal value is 9. CEBM is widely used because of decoding simply and small hardware overhead.
Through the analysis, the scheme has the following three characteristics. (1) The root number is calculated from 2 and increases successively. It can guarantee that the radicand and root number found are minimum. (2) The lower bound and upper bound of the radicand’s interval positioned are relatively accurate. At the same time, the binary search method can reduce the time complexity. (3) In the binary search, the medians of the operation process are all integers. It can reduce the computation complexity, save the running time, and accelerate the process of operation.
2.2. Encoding Example
An example is provided to make the scheme clear. Without loss of generality, set the original test set . Cascade all the test vector, and then divide it into sequences of 48 bits. The data flow is 000110101110100010011111100110010101101011010011 11101001… . Its first 48 bits can convert into a hexadecimal floatingpoint .AE89F995AD3. (I) Calculate .D413CCCFE7551FCA6F09E9, , , . (II) Calculate .BB67AE8584C, and go to step (III) because its value is not equal to . (III) Consider , , . (IV) Set , and calculate . If its value is equal to , note , , and go to step of encoding. If its value is greater than , set . If its value is less than , set . Repeat step (IV) until , and go to step (V). (V) If is less than , set , . Otherwise, set , . Then , . Repeat steps (III), (IV), and (V) and we can get the results , , which make .AE89F995AD3. So the storage of the first 48 bits of the data flow 00011010111010001001111110011001010110101101001111101001… can be converted into the storage of the radicand (8) and the root number (4). The CEBM of 8 and 4 is 000001 0001, a total of 10 bits, reducing 38 bits.
3. Theoretical Analysis
In this section, the theoretical analysis of the algorithm is given.
For any floatingpoint number , there exist positive integers , , which make the first several bits of and the root of to be exactly the same; that is to say, the two are approximately equal.
The process of proof is as follows.
From the encoding rule of Section 2.1, is positioned in the interval [, ] through binary search each time in the process of successive approximation, where
Therefore, we only need to prove that is infinitely close to when . That is to prove
That is to say, we can always find positive integers and to make and to be approximately equal when is increasing.
4. Structure of Decompressor
In this section, the structure and basic operation principle of the decompressor for the INS coding scheme are illustrated.
Figure 2 shows the structure of decompressor, which contains a finite state machine, a T flipflop, a special bits counter and some combinational logic, and the CPU module on SoC chip.
This special bits counter is unique. Set its lowest bit as 1; move this bit to high with other data when the data needed to be decoded is moved to the counter. The function can be realized by a combination of some simple circuit, and the hardware overhead will not increase significantly. In the bits counter, the value of is decided by the maximum of the radicand and the boot number (named as ) in compression result, .
The root operation can be realized by the CPU module on SoC chip as long as the floatingpoint processing unit ×87 FPU integrated in CPU. ×87 FPU has its own instruction system, including the commonly used instruction types: floatingpoint move instructions, floatingpoint arithmetic operation instructions, floatingpoint transcendental function instructions, floatingpoint comparison instructions, and FPU control instructions [11]. Floatingpoint transcendental function instructions can realize exponent operation (F2XM1 instruction) and logarithmic operation (FYL2X instruction). can be converted into , which can be calculated by exponent operation instruction and logarithmic operation instruction.
Decompressor works as follows. (1) First, the FSM makes an enable signal named en into high level, and the encoded data named bit_in is split into two parts: odd bits and even bits by the position of data. That is implemented by the T flipflop. Odd bits are directly shifted into the bits counter, and even bits are shifted into FSM. (2) Then, FSM repeats to read the encoded data until the value of even bit equals 1. Meanwhile, the odd bit is shifted into the bits counter. (3) The data (named ) of the bits counter is shifted into CPU after all odd bits of data are received in the special bits counter. Repeat step (2); the data of the bits counter (named ) is shifted into CPU. (4) is calculated by floatingpoint processing unit ×87 FPU in CPU, and the first bits of its binary form are outputted.
5. Experimental Results
In this section, the effectiveness of the INS coding scheme is verified by using experimental results.
INS coding is applied to the MinTest test sets of the largest ISCAS 89 benchmark circuits. The experimental results are shown in Table 3. The first column shows the circuit name, the second column shows the total number of the data in the original test sets, the third column shows the total number of the compressed data, and the fourth column shows the compression ratio.

In order to verify the validity of this scheme, compare with the similar algorithm, as shown in Table 4. Among them, the first column shows the circuit name, the second to sixth columns, respectively, show the compression effect of FDR code [6], INDC code [9], AARLC code [8], FAVLC code [12], and VRL code [13], and the seventh column shows compression effect of the scheme presented. Data from Table 3 shows this scheme besides lower compression ratio in the fifth circuit, and the rest of the circuit has higher compression ratio. And this scheme has a good compression effect on the whole. The average compression ratio reaches 65.79%, which is 20.46%, 9.42%, 7.36%, 5.36%, and 1.85% higher than those of FDR, RLR, AARLC, FAVLC, and VRL.

In order to further demonstrate the effectiveness, the results of proposed scheme are compared with other schemes under the same circumstances by the hard fault set of some ISCAS 89 benchmark circuits. The results as shown in Table 5. As can be seen from Table 4, the overall effect of proposed scheme is better. The average compression ratio of the proposed scheme is 3.87%, 3.82%, and 3.31% higher than those of FDR, AR [14], and ARL [15]. These data show the effectiveness of INS Code.

The experimental results indicate the following. (1) Regardless of the fact that the determined bit of the test data is 0 or 1, it has a little effect on compression ratio in the process of finding the irrational number. (2) Do notcare bit can accelerate the search speed of irrational number, reduce the value of irrational number used to store the test data, and improve the compression ratio.
The influence of the do notcare bit probability on compression is explored. The length of the test data fragment is set to be , and the probability of do notcare bit is set to be . Their relationship can be expressed in the following formula: where, , , and are integers and is a floatingpoint number.
The compression gain can be calculated by the following formula:
By analyzing the experimental data, the relationship between the compression gain and the probability of notcare bit can be concluded as shown in Figure 3.
From Figure 3, as can be seen, the proposed compression scheme can obtain better compression effect in a higher probability of do notcare bit.
6. Conclusion
INS coding is presented, which uses the floatingpoint number unfolded by irrational number to store the test set. It is creative. Using the successive approximation method can accelerate the convergence speed in the process of searching the irrational number. The experimental results show that the compression effect of the scheme is better. It provides a new choice to solve the problem of test data compression.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
Acknowledgments
The authors sincerely thank the anonymous reviewers for their valuable and constructive comments. This research is supported in part by the Natural Science Foundation of China (no. 61306046) and Scientific Research Foundation of High Institutions in Anhui Province (no. KJ2012B082).
References
 L. Li, K. Chakrabarty, S. Kajihara, and S. Swaminathan, “Efficient space/time compression to reduce test data volume and testing time for IP cores,” in Proceedings of the 18th International Conference on VLSI Design, pp. 53–58, January 2005. View at: Publisher Site  Google Scholar
 A. Jas, J. GhoshDastidar, M. Ng, and N. A. Touba, “An efficient test vector compression scheme using selective huffman coding,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 797–806, 2003. View at: Publisher Site  Google Scholar
 M. Tehranipoor, M. Nourani, and K. Chakrabarty, “Ninecoded compression technique for testing embedded cores in SoCs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp. 719–731, 2005. View at: Publisher Site  Google Scholar
 A. Jas and N. A. Touba, “Test vector decompression via cyclical scan chains and its application to testing corebased designs,” in Proceedings of the IEEE International Test Conference, pp. 458–464, Washington, DC, USA, October 1998. View at: Google Scholar
 A. Chandra and K. Chakrabarty, “Systemonachip testdata compression and decompression architectures based on Golomb codes,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 20, no. 3, pp. 355–368, 2001. View at: Publisher Site  Google Scholar
 A. Chandra and K. Chakrabarty, “Frequencydirected runlength (FDR) codes with application to systemonachip test data compression,” in Proceedings of the 19th IEEE VLSI Test Symposium, pp. 42–47, Marina Del Rey, Calif, USA, May 2001. View at: Google Scholar
 A. H. ElMaleh, “Test data compression for systemonachip using extended frequencydirected runlength code,” IET Computers and Digital Techniques, vol. 2, no. 3, pp. 155–163, 2008. View at: Publisher Site  Google Scholar
 H. G. Liang and C. Y. Jiang, “Efficient test data compression and decompression based on alternation and run length codes,” Chinese Journal of Computers, vol. 27, no. 4, pp. 548–554, 2004. View at: Google Scholar  MathSciNet
 W. Haifeng, Z. Wenfa, and C. Yifei, “Scheme of test data compression based on irrational number dictionary code,” Computer Engineering and Applications, vol. 50, no. 7, pp. 235–237, 2014. View at: Google Scholar
 W. Zhan, H. Liang, C. Jiang, Z. Huang, and A. ElMaleh, “A scheme of test data compression based on coding of even bits marking and selective output inversion,” Computers & Electrical Engineering, vol. 36, no. 5, pp. 969–977, 2010. View at: Publisher Site  Google Scholar
 X.J. Qian, 32Bits Assembly Language Programming, China Machine Press, Beijing, China, 2011.
 W.F. Zhan, H.G. Liang, F. Shi, and Z.F. Huang, “Test data compression scheme based on mixed fixed and variable length coding,” Chinese Journal of Computers, vol. 31, no. 10, pp. 1826–1834, 2008. View at: Google Scholar
 X.Y. Peng and Y. Yu, “A test set compression algorithm based on VariableRunLength code,” Acta Electronica Sinica, vol. 35, no. 2, pp. 197–201, 2007. View at: Google Scholar
 A. Chandra and K. Chakrabarty, “Reduction of SOC test data volume, scan power and testing time using alternating runlength codes,” in Proceedings of the 39th Annual Design Automation Conference (DAC '02), pp. 673–678, June 2002. View at: Publisher Site  Google Scholar
 S. Hellebrand and A. Wurternberger, “Alternating runlength coding—a technique for improved test data compression,” in Proceedings of the 3rd IEEE International Workshop on Test Tesource Partitioning (TRP '02), IEEE Computer Society, Baltimore, Md, USA, October 2002. View at: Google Scholar
Copyright
Copyright © 2014 Haifeng Wu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.