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VLSI Design
Volume 1 (1994), Issue 4, Pages 277-284
http://dx.doi.org/10.1155/1994/27973

Resolution Enhancement in IDDQ Testing for Large ICs

1Dept. of Computer Science, Colorado State University, Ft. Collins, CO, USA
2Dept. of Electrical Engineering, Colorado State University, Ft. Collins, CO, USA

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • A Ferré, E Isern, J Rius, R Rodri´guez-Montañés, and J Figueras, “IDDQ testing: state of the art and future trends,” Integration, the VLSI Journal, vol. 26, no. 1-2, pp. 167–196, 1998. View at Publisher · View at Google Scholar
  • W. Jiang, and B. Vinnakota, “Statistical threshold formulation for dynamic I/sub dd/ test,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 6, pp. 694–705, 2002. View at Publisher · View at Google Scholar