Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 1, Issue 4, Pages 277-284
http://dx.doi.org/10.1155/1994/27973

Resolution Enhancement in IDDQ Testing for Large ICs

1Dept. of Computer Science, Colorado State University, Ft. Collins, CO, USA
2Dept. of Electrical Engineering, Colorado State University, Ft. Collins, CO, USA

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [8 citations]

The following is the list of published articles that have cited the current article.

  • A. Ferre, and J. Figueras, “I/sub DDQ/ characterization in submicron CMOS,” Proceedings International Test Conference 1997, pp. 136–145, . View at Publisher · View at Google Scholar
  • W. Jiang, and B. Vinnakota, “Statistical threshold formulation for dynamic I/sub dd/ test,” International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp. 57–66, . View at Publisher · View at Google Scholar
  • A. Ferre, and J. Figueras, “On estimating bounds of the quiescent current for I/sub DDQ/ testing,” Proceedings of 14th VLSI Test Symposium, pp. 106–111, . View at Publisher · View at Google Scholar
  • S. Sabade, and H. Walker, “Evaluation of statistical outlier rejection methods for I/sub DDQ/ limit setting,” Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, pp. 755–760, . View at Publisher · View at Google Scholar
  • M. Rullan, C. Ferrer, J. Oliver, D. Mateo, and A. Rubio, “Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design,” Proceedings ED&TC European Design and Test Conference, pp. 584–588, . View at Publisher · View at Google Scholar
  • C. Thibeault, “An histogram based procedure for current testing of active defects,” International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp. 714–723, . View at Publisher · View at Google Scholar
  • A Ferré, E Isern, J Rius, R Rodri´guez-Montañés, and J Figueras, “IDDQ testing: state of the art and future trends,” Integration, the VLSI Journal, vol. 26, no. 1-2, pp. 167–196, 1998. View at Publisher · View at Google Scholar
  • W. Jiang, and B. Vinnakota, “Statistical threshold formulation for dynamic I/sub dd/ test,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 6, pp. 694–705, 2002. View at Publisher · View at Google Scholar