Built-in-self-test (BIST) response data can be compacted using a linear-feedback shift register (LFSR). Prior workhas indicated that the probability of aliasing tends to converge to 2-k for a polynomial of degree k and large testlength, and that primitive polynomials perform better than non-primitive polynomials. Nearly all analytical modelsand simulations have been based on the assumption that error occurrences are statistically-independent. Thispaper presents the first statistical results, based on fault simulation, that show that this convergence propertyholds for actual digital logic circuits and randomly-generated test vector sequences. However, it is shown thatthe average probability of aliasing is unsuitable as a design metric, and that a 95&#37; upper confidence limit (UCL)is more useful. This paper introduces a UCL for the loss of fault coverage due to test response compaction. Thetheoretical or &#8220;ideal&#8221; UCL is shown to match closely the empirically-derived UCL obtained by fault simulation.The result is that a tight lower bound on fault coverage for LFSR-based BIST configurations can be obtainedeasily. Fault coverage for a BIST configuration can be obtained without the LFSR, eliminating costly faultsimulation of the full structure with the LFSR. These results have been incorporated in the standard procedurefor fault coverage measurement.

Warren H. Debany

Mark J. Gorniak

Anthony R. Macera

Daniel E. Daskiewich

Kevin A. Kwiat

Heather B. Dussault

Empirical Bounds on Fault Coverage LossDue to LFSR Aliasing

While the performance, density, and complexity of application-specific systems increase at a rapid pace, equivalent
advances are not being made in making them more easily testable, diagnosable, and maintainable. Even though
testability bus standards, like JTAG Boundary Scan, have been developed to help eliminate these costs, there
exists a need for efficient hardware and software tools to support them. Hence, a testability design and hardware
support environment for application-specific systems is described which provides a designer with a set of hardware
modules and circuitry, that support these standards and software tools for automatic incorporation of testability
hardware, as well as automatic test vector and test program generation.

Kevin T. Kornegay

Robert W. Brodersen

Integrated Test Solutions for a System Design
Environment

Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the manyDFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paperwe explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flopsand obtain reasonably high coverage. This approach has lower overhead in terms of test application timeand hardware area when compared to previous ones. Further enhancement of the controllability is obtained byusing multiple reset lines. The configuration of these multiple reset lines is described. This technique has beenevaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.

Ben  Mathew

Daniel G. Saab

Partial Reset: An Alternative DFT Approach

The logic behavior and performance of ECL gates under a set of defect models are examined. These are comparedwith equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaininga sufficiently high fault coverage, e.g., 79&#37; for ECL versus 54&#37; for BiCMOS and 69&#37; for CMOS equivalentgates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or NoiseMargin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay faulttesting yields the highest fault coverage for BiCMOS and CMOS gates (around 95&#37;). However, for equivalentECL gates to attain a fault coverage of around 98&#37;, both logical and NM fault testing have to be used.

M. O. Esonu

D.  Al-Khalili

C.  Rozon

Fault Characterization and Testability Analysis ofEmitter Coupled Logic and Comparison with CMOS&#38; BiCMOS Circuits

On-the-fly calculations of area and performance are a typical part of the computer-aided iterative design processin VLSI, which aims at a satisfactory tradeoff of various conflicting objectives, among which are test-generationtime and test-set size. However, determining test sets on-the-fly as one circuit is transformed into another isextremely difficult. Our goal is to add a test dimension to the design optimization process that complementsmethods concerned with area and performance optimization. We define a set of logic transformations that resultin easily computed changes to test sets. Test-set preserving (TSP) transformations preserve a combinational circuit’stest sets, while test-set altering (TSA) transformations introduce a minimum number of tests needed to maintaincompleteness. We illustrate our approach with a family of adders that share area-efficient tree structures anddiffer in the amount of carry-lookahead used to accelerate carry computation. Members include the ripple-carryadder, which has no lookahead, and the standard carry-lookahead adder, which exploits lookahead across allinputs. It is straightforward to derive area and performance measures for this class of adders. Given an n-bitadder with lookahead degree k, we determine a sequence of circuit transformations that produce the adder ofdegree k2 and test sets of minimum size. Optimal test sets of size k(logkn + 1) + 2 result for arbitrary n and k,which improve significantly upon previously reported tests.

Michael J. Batek

John P. Hayes

Optimal Testing and Design of Adders

Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and isnormally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Manyfaults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders ofmagnitude. Some of these faults may not manifest themselves as logical faults, and would not be detected bytraditional IC test techniques.In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due tonormal parameter variations. A statistical characterization of the problem is presented. This can be used todetermine the optimal size of partitions. A new information compression scheme is presented which can significantlyenhance resolution.

Yashwant K. Malaiya

Anura P. Jayasumana

Carol Q. Tong

Sankaran M. Menon

Resolution Enhancement in IDDQ Testingfor Large ICs

This paper presents a technique for designing interacting finite state machines which will be totally self-checking
for any single stuck-at fault. In the proposed technique m-out-of-n codes are used for both primary output and
state assignments. In addition, the next state logic (NSL) for each submachine and the output logic (OL) are
realized such that any single stuck-at fault results in either single bit error or unidirectional multibit error at the
output. The proposed technique does not have any restriction on the way the NSL and the OL are implemented.

Fadi Busaba

Parag K. Lala

An Approach for Self-Checking Realization of
Interacting Finite State Machines

We present a design method (called STD architecture) to design large memories so that the test time does notincrease with the increasing size of memory. Large memories can be constructed by using several small blocksof memory. The memory address decoder is divided into two or more levels and designed such that during thetest mode all small memory blocks are accessed together. With the help of modified decoder, all small memoryblocks are tested in parallel using any standard test algorithm. In this design, time to test the whole memory isequal to the time required to test one small block. The proposed design is highly structured and hardware overheadis negligible. The basic idea is to exploit internal hardware for testing purpose. With the proposed method aconstant test time can be achieved irrespective of the memory size. STD architecture is applicable to memorychips as well as memory boards, and the design is suitable for fault detection as well as for fault diagnosis.

Rochit  Rajsuman

Kamal  Rajkanan

STD Architecture: A Practical Approach to TestM-Bits Random Access Memories

Rochit   Rajsuman

Special Issue on Digital Hardware Testing

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