VLSI Design

Digital Hardware Testing


Status
Published

Guest Editors
Rochit Rajsuman

Digital Hardware Testing

Articles

  • Special Issue
  • - Volume 1
  • - Article ID 070696

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits

M. O. Esonu | D. Al-Khalili | C. Rozon
  • Special Issue
  • - Volume 1
  • - Article ID 078932

Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing

Warren H. Debany | Mark J. Gorniak | ... | Heather B. Dussault
  • Special Issue
  • - Volume 1
  • - Article ID 039791

Integrated Test Solutions for a System Design Environment

Kevin T. Kornegay | Robert W. Brodersen
  • Special Issue
  • - Volume 1
  • - Article ID 031646

Partial Reset: An Alternative DFT Approach

Ben Mathew | Daniel G. Saab
  • Special Issue
  • - Volume 1
  • - Article ID 074269

Optimal Testing and Design of Adders

Michael J. Batek | John P. Hayes
  • Special Issue
  • - Volume 1
  • - Article ID 027973

Resolution Enhancement in IDDQ Testing for Large ICs

Yashwant K. Malaiya | Anura P. Jayasumana | ... | Sankaran M. Menon
  • Special Issue
  • - Volume 1
  • - Article ID 082606

An Approach for Self-Checking Realization of Interacting Finite State Machines

Fadi Busaba | Parag K. Lala
  • Special Issue
  • - Volume 1
  • - Article ID 024312

Special Issue on Digital Hardware Testing

Rochit Rajsuman
  • Special Issue
  • - Volume 1
  • - Article ID 036218

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories

Rochit Rajsuman | Kamal Rajkanan