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VLSI Design
Volume 1 (1994), Issue 4, Pages 299-311

Partial Reset: An Alternative DFT Approach

Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, USA

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the many DFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paper we explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flops and obtain reasonably high coverage. This approach has lower overhead in terms of test application time and hardware area when compared to previous ones. Further enhancement of the controllability is obtained by using multiple reset lines. The configuration of these multiple reset lines is described. This technique has been evaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.