VLSI Design

VLSI Design / 1994 / Article
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Digital Hardware Testing

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Volume 2 |Article ID 037474 | https://doi.org/10.1155/1994/37474

A. Mahmood, J. Herath, J. Jayasumana, "An Improved Data Flow Architecture for Logic Simulation Acceleration", VLSI Design, vol. 2, Article ID 037474, 7 pages, 1994. https://doi.org/10.1155/1994/37474

An Improved Data Flow Architecture for Logic Simulation Acceleration

Received31 Aug 1991
Revised11 Apr 1992

Abstract

The high degree of parallelism in the simulation of digital VLSI systems can be utilized by a data flow architecture to reduce the enormous simulation times. The existing logic simulation accelerators based on the data flow principle use a static data flow architecture along with a timing wheel mechanism to implement the event driven simulation algorithm. The drawback in this approach is that the timing wheel becomes a bottleneck to high simulation throughput. Other shortcomings of the existing architecture are the high communication overhead in the arbitration and distribution networks, and reduced pipelining due to a static data flow architecture. To overcome these, three major improvements are made to the design of a classical data flow based logic simulation accelerator. These include:1) A novel and efficient technique for implementing a pseudo-dynamic data flow architecture to increase pipelining.2) Implementation of a modified distributed event driven simulation algorithm.3) Localized processors for fast evaluation of small primitives.

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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